Method of forming a via plug in a semiconductor device

Abstract

A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.

What is claimed is: 
     
       1. A method of forming a via plug in a semiconductor device comprises; forming a first metal layer on a substrate and sequentially depositing a first, second and third insulating layer on the resulting substrate and then planarizing said third insulating layer;   etching a desired portion of said third, second and first insulating layer using a contact mask until said first metal layer is exposed, thereby forming a via hole;   pretreating said via hole by the dry etching method and then, forming metal nuclei on the surface of said first metal layer at the bottom of said via hole;   etching said first metal layer exposed between said metal nuclei so that a plurality of etching grooves is formed on said first metal layer; and   forming a via plug on said via hole.   
     
     
       2. The method of claim 1, wherein said first metal layer exposed between said metal nuclei is etched by .[.the.]. .Iadd.a .Iaddend.wet etchant which .[.the.]. .Iadd.an .Iaddend.etching selectivity of said first metal layer is greater than said that of said metal nuclei. 
     
     
       3. The method of claim 1, wherein said via plug is formed in .[.the.]. .Iadd.an .Iaddend.LPCVD reactor. 
     
     
       4. The method of claim 1, wherein .[.the.]. .Iadd.a .Iaddend.magnitude of each nuclei is 500 to 1000 Å. 
     
     
       5. The method of claim 1, wherein said via hole is pretreated in .[.the.]. .Iadd.a .Iaddend.RIE reactor. 
     
     
       6. The method of claim 1, wherein said via hole is pretreated by a NF 3 , SF 6  or Ar sputter. 
     
     
       7. The method of claim 1, wherein said etching grooves are formed using .[.the.]. .Iadd.a .Iaddend.buffered oxide etchant. 
     
     
       8. The method of claim 1, wherein said metal nuclei are formed by tungsten. 
     
     
       9. The method of claim 1, wherein said metal nuclei are formed by aluminum. 
     
     
       10. The method of claim 1, wherein said metal nuclei are formed by copper. 
     
     
       11. The method of claim 1, wherein said metal nuclei are formed by molybdenum. 
     
     
       12. The method of claim 1, wherein said metal nuclei are formed by titanium. 
     
     
       13. The method of claim 1, wherein said metal nuclei are formed by cobalt. 
     
     
       14. The method of claim 1, wherein said metal nuclei are formed by chromium. .Iadd. 
     
     
       15.  A method of forming a via plug in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves are formed by a buffered oxide etching process; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.   
     
     
       16.  The method of claim 15, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.17. The method of claim 15, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.18. The method of claim 15, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.19. The method of claim 15, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.20. The method of claim 19, wherein said third insulating layer is planarized..Iaddend..Iadd.21. The method of claim 15, wherein said insulating layer is planarized..Iaddend..Iadd.22. The method of claim 15, wherein said metal nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.23. The method of claim 15, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.24. The method of claim 15, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.25. The method of claim 15, wherein said increased surface area increases an 
     
     
        adhesive strength..Iaddend..Iadd.26.  A method of forming a via plug in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.27. The method of claim 26, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.28. The method of claim 26, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.29. The method of claim 26, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.30. The method of claim 26, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.31. The method of claim 26, wherein said metal nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.32. The method of claim 26, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.33. The method of claim 26, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.34. The method of claim 26, wherein said increased   
     
     
        surface area reduces a via resistance..Iaddend..Iadd.35.  The method of claim 26, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.36. The method of claim 26, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.37. A method of forming a via plug in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming metal nuclei and a plurality of grooves adjacent to said metal nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.38. The method of claim 37, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.39. The method of claim 37, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.40. The method of claim 37, wherein said metal nuclei are formed by a process including deposition..Iaddend..Iadd.41. The method of claim 37, wherein said insulating layer comprises a first insulating layer over said conductive layer and a second insulating layer over said first insulating layer..Iaddend..Iadd.42. The method of claim 37, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.43. The method of claim 37, wherein said insulating layer is planarized..Iaddend..Iadd.44. The method of claim 37, wherein said metal nuclei comprises material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and   
     
     
        chromium..Iaddend..Iadd.45.  The method of claim 37, wherein each of said metal nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.46. The method of claim 37, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.47. The method of claim 37, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.48. A method of forming a plug layer in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.49. The method of claim 48, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.50. The method of claim 48, wherein said conductive nuclei are formed by a process including deposition..Iaddend..Iadd.51. The method of claim 48, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.52. The method of claim 48, wherein said insulating layer is planarized..Iaddend..Iadd.53. The method of claim 48, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt,   
     
     
        and chromium..Iaddend..Iadd.54.  The method of claim 48, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.55. The method of claim 48, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.56. The method of claim 48, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.57. The method of claim 48, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.58. The method of claim 57, wherein said third insulating layer is planarized..Iaddend..Iadd.59. A method of forming a plug layer in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.60. The method of claim 59, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.61. The method of claim 59, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.62. The method of claim 59, wherein said conductive nuclei are formed by a process including deposition..Iaddend..Iadd.63. The method of claim 59, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is   
     
     
        over and in contact with said first insulating layer..Iaddend..Iadd.64. The method of claim 59, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.65. The method of claim 59, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.66. The method of claim 59, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.67. The method of claim 59, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.68. The method of claim 59, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.69. The method of claim 59, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.70. A method of forming a plug layer in a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming conductive nuclei and a plurality of grooves adjacent to said conductive nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.71. The method of claim 70, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.72. The method of claim 70, wherein said plurality of grooves are formed by a wet etching process..Iaddend..Iadd.73. The method of claim 70, wherein said conductive nuclei are formed by a   
     
     
        deposition process..Iaddend..Iadd.74.  The method of claim 70, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.75. The method of claim 70, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.76. The method of claim 70, wherein said insulating layer is planarized..Iaddend..Iadd.77. The method of claim 70, wherein said conductive nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.78. The method of claim 70, wherein each of said conductive nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.79. The method of claim 70, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.80. The method of claim 70, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.81. A method of forming a plug layer in a semiconductor device, comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.82. The method of claim 81, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.83. The method of claim 81, wherein said   
     
     
        nuclei are formed by a process including deposition..Iaddend..Iadd.84. The method of claim 81, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.85. The method of claim 81, wherein said insulating layer is planarized..Iaddend..Iadd.86. The method of claim 81, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.87. The method of claim 81, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.88. The method of claim 81, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.89. The method of claim 81, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.90. The method of claim 81, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.91. The method of claim 90, wherein said third insulating layer is planarized..Iaddend..Iadd.92. A method of forming a plug layer in a semiconductor device, comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.93. The method of claim 92, further comprising pretreating said exposed portion of said conductive layer by an etching method..Iaddend..Iadd.94. The method of claim 92, wherein said plurality of grooves are formed by a process including wet   
     
     
        etching..Iaddend..Iadd.     The method of claim 92, wherein said nuclei are formed by a process including deposition..Iaddend..Iadd.96. The method of claim 92, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.97. The method of claim 92, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.98. The method of claim 92, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.99. The method of claim 92, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.100. The method of claim 92, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.101. The method of claim 92, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.102. The method of claim 92, wherein said insulating layer further comprises a third insulating layer overlying said second insulating 
     
     
        layer..Iaddend..Iadd.103.  A method of forming a plug layer in a semiconductor device, comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming nuclei and a plurality of grooves adjacent to said nuclei on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.104. The method of claim 103, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.105. The method of claim 103, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.106. The method of claim 103, wherein said nuclei are formed by a process including deposition..Iaddend..Iadd.107. The method of claim 103, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.108. The method of claim 103, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.109. The method of claim 103, wherein said insulating layer is planarized..Iaddend..Iadd.110. The method of claim 103, wherein said nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium..Iaddend..Iadd.111. The method of claim 103, wherein each of said nuclei has a magnitude of 500 to 1,000 Å..Iaddend..Iadd.112. The method of claim 103, wherein said increased surface area reduces a via   
     
     
        resistance..Iaddend..Iadd.113.  The method of claim 103, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.114. A method of forming a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.115. The method of claim 114, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.116. The method of claim 114, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.117. The method of claim 114, wherein said insulating layer is planarized..Iaddend..Iadd.118. The method of claim 114, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.119. The method of claim 114, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.120. The method of claim 114, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.121. The method of claim 120, wherein said third insulating layer is planarized..Iaddend..Iadd.122. A method of forming a semiconductor device comprising:   providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.123. The method of claim 122, further comprising pretreating said exposed portion of said conductive layer by a process   
     
     
        including etching..Iaddend..Iadd.124.  The method of claim 122, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.125. The method of claim 122, wherein said first insulating layer is over and in contact with said conductive layer and said second insulating layer is over and in contact with said first insulating layer..Iaddend..Iadd.126. The method of claim 122, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.127. The method of claim 122, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.128. The method of claim 122, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.129. The method of claim 122, wherein said insulating layer further comprises a third insulating layer over said second insulating layer..Iaddend..Iadd.130. A method of forming a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase surface area of said conductive layer, wherein said plurality of grooves is formed by etching; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.131. The method of claim 130, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.132. The method of claim 130, wherein said plurality of grooves are formed by a process including wet   
     
     
        etching..Iaddend..Iadd.133.  The method of claim 130, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.134. The method of claim 130, wherein said insulating layer is planarized..Iaddend..Iadd.135. The method of claim 130, wherein said increased surface area reduces a via resistance..Iaddend..Iadd.136. The method of claim 130, wherein said increased surface area increases an adhesive strength..Iaddend..Iadd.137. The method of claim 130, wherein said insulating layer comprises a first insulating layer over said conductive layer, a second insulating layer over said first insulating layer, and a third insulating layer over said second insulating layer..Iaddend..Iadd.138. A method of forming a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer, wherein said plurality of grooves is formed by a buffered oxide etching process; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.139. The method of claim 138, comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.140. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.141. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.142. The method of claim 138, wherein said   
     
     
        insulating layer is planarized..Iaddend..Iadd.143.  The method of claim 138, wherein said increased adhesive strength reduces a via resistance..Iaddend..Iadd.144. The method of claim 138, wherein said insulating layer comprises a first insulating layer overlying and in contact with said conductive layer, a second insulating layer overlying and in contact with said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.145. The method of claim 144, wherein said third insulating layer is planarized..Iaddend..Iadd.146. A method of forming a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.147. The method of claim 146, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.148. The method of claim 146, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.149. The method of claim 146, wherein said first insulating layer is over said conductive layer and said second insulating layer is over said first insulating layer..Iaddend..Iadd.150. The method of claim 146, wherein said plurality of grooves is formed by a process including etching..Iaddend..Iadd.151. The method of claim 146, wherein said increased adhesive strength reduces a via resistance..Iaddend..Iadd.152. The method of claim 146, wherein said insulating layer further comprises a third insulating layer over said   
     
     
        second insulating layer..Iaddend..Iadd.153.  A method of forming a semiconductor device comprising: providing a substrate;   forming a conductive layer overlying said substrate;   forming an insulating layer overlying said conductive layer;   forming a via structure in said insulating layer, which exposes a portion of said conductive layer;   forming a plurality of grooves on said conductive layer within said exposed portion of said conductive layer to increase adhesive strength of said conductive layer, wherein said plurality of grooves is formed by etching; and   forming a plug layer overlying said exposed portion in said via structure..Iaddend..Iadd.154. The method of claim 153, further comprising pretreating said exposed portion of said conductive layer by a process including etching..Iaddend..Iadd.155. The method of claim 153, wherein said plurality of grooves are formed by a process including wet etching..Iaddend..Iadd.156. The method of claim 153, wherein said insulating layer comprises a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer..Iaddend..Iadd.157. The method of claim 153, wherein said insulating layer comprises a first insulating layer overlying said conductive layer, a second insulating layer overlying said first insulating layer, and a third insulating layer overlying said second insulating layer..Iaddend..Iadd.158. The method of claim 153, wherein said insulating layer is planarized..Iaddend..Iadd.159. The method of claim 153, wherein said increased adhesive strength reduces a via resistance..Iaddend.