Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer

Abstract

A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography techniques. The method can also be used to create sharp emission tips for field effect display devices.

What is claimed is: 
     
       1. A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer;   b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm);   c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;   d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;   e. depositing a conformal mask material over the first layer and void;   f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material;   g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.   
     
     
       2. The method of claim 1 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm. 
     
     
       3. The method of claim 1 wherein the first layer is a mask oxide. 
     
     
       4. The method of claim 1 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       5. The method of claim 1 wherein the conformal mask material is polysilicon. 
     
     
       6. The method of claim 2 wherein the width of the submicron line is less than 0.15 μm. 
     
     
       7. A method for fabricating close-tolerance, sharp emission tip on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer;   b. forming a loose-tolerance trench in the first layer having a diameter of less than 1 micrometer (μm);   c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;   d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;   e. depositing a conformal mask material over the first layer and void;   f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material;   g. isotropically etching by a photolithography process the first layer and non-conformal material thereby forming the sharp emission tip below the conformal mask material having a lesser diameter than the loose-tolerance well.   
     
     
       8. The method of claim 7 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter. 
     
     
       9. The method of claim 7 wherein the first layer is a mask oxide. 
     
     
       10. The method of claim 7 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       11. The method of claim 7 wherein the conformal mask material is polysilicon. 
     
     
       12. The method of claim 8 wherein the diameter of the sharp emission tip is less than 0.15 μm. 
     
     
       13. A method for fabricating close-tolerance mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer;   b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm);   c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;   d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;   e. depositing a conformal mask material over the first layer and void; and then   f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material.   
     
     
       14. The method of claim 13 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm. 
     
     
       15. The method of claim 13 wherein the first layer is a mask oxide. 
     
     
       16. The method of claim 13 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       17. The method of claim 13 wherein the conformal mask material is polysilicon. 
     
     
       18. The method of claim 14 wherein the width of the mask is less than 0.15 μm. 
     
     
       19. A method for fabricating close-tolerance, circular mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer;   b. forming a loose-tolerance well in the first layer having a width of less than 1 micrometer (μm);   c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the well, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;   d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;   e. depositing a conformal mask material over the first layer and void; and then   f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material.   
     
     
       20. The method of claim 19 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter. 
     
     
       21. The method of claim 19 wherein the first layer is a mask oxide. 
     
     
       22. The method of claim 19 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride. 
     
     
       23. The method of claim 19 wherein the conformal mask material is polysilicon. .Iadd. 
     
     
       24.  A method for fabricating at least one submicron line on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising: depositing a first layer on top of the polysilicon layer;   forming a trench in the first layer;   depositing a non-conformal material over the first layer to form a void in the trench;   removing the non-conformal material down to a top surface of the first layer to expose the void;   depositing a conformal mask material over the first layer and void;   removing the conformal mask material above the first layer; and   etching the first layer and non-conformal material..Iaddend..Iadd.25. The method of claim 24 wherein the trench includes a width of less than 1 μm..Iaddend..Iadd.26. The method of claim 24 wherein the trench is between 0.40 μm and 0.7 μm in width..Iaddend..Iadd.27. The method of claim 24 wherein the first layer is a mask oxide..Iaddend..Iadd.28. The method of claim 24 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.29. The method of claim 24 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.30. The method of claim 24 wherein the conformal mask material is polysilicon..Iaddend..Iadd.31. The method of claim 24 wherein   
     
     
        the submicron line is less than 0.15 μm in width..Iaddend..Iadd.32. The method of claim 24 wherein the void includes a tear-drop shaped cross section..Iaddend..Iadd.33. The method of claim 24 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.34. The method of claim 24 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.35. The method of claim 24 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.36. A method for fabricating at least one sharp emission tip on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising: depositing a first layer on top of the polysilicon layer;   forming a well in the first layer;   depositing a non-conformal material over the first layer to form a void in the well;   removing the non-conformal material down to a top surface of the first layer to expose the void;   depositing a conformal mask material over the first layer and void;   removing the conformal mask material above the first layer; and   etching the first layer and non-conformal material..Iaddend..Iadd.37. The method of claim 36 wherein the well includes a diameter of less than 1 μm..Iaddend..Iadd.38. The method of claim 36 wherein the well is between 0.40 μm and 0.7 μm in diameter..Iaddend..Iadd.39. The method   
     
     
        of claim 36 wherein the first layer is a mask oxide..Iaddend..Iadd.40. The method of claim 36 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.41. The method of claim 36 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.42. The method of claim 36 wherein the conformal mask material is polysilicon..Iaddend..Iadd.43. The method of claim 36 wherein the sharp emission tip is less than 0.15 μm in diameter..Iaddend..Iadd.44. The method of claim 36 wherein the void includes a tear-drop shape..Iaddend..Iadd.45. The method of claim 36 wherein removing the non-conformal mask material down to a top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.46. The method of claim 36 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.47. The method of claim 36 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.48. The method of claim 36 wherein etching the first layer and non-conformal material 
     
     
        includes an isotropic etch..Iaddend..Iadd.49.  A method for fabricating a mask on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising: depositing a first layer on top on the polysilicon layer;   forming an opening in the first layer;   depositing a non-conformal material over the first layer to form a void in the opening;   removing the non-conformal material down to a top surface of the first layer to expose the void;   depositing a conformal mask material over the first layer and void; and   removing the conformal mask material above the first layer..Iaddend..Iadd.50. The method of claim 49 wherein the first layer is a mask oxide..Iaddend..Iadd.51. The method of claim 49 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride..Iaddend..Iadd.52. The method of claim 49 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.53. The method of claim 49 wherein the conformal mask material is polysilicon..Iaddend..Iadd.54. The method of claim 49 wherein the opening includes a trench..Iaddend..Iadd.55. The method of claim 54 wherein the trench is less than 1 μm in width..Iaddend..Iadd.56. The method of claim 54 wherein the trench is between 0.40 μm and 0.7 μm in width..Iaddend..Iadd.57. The method of claim 54 wherein the mask is less than 0.15 μm in width..Iaddend..Iadd.58. The method of claim 49 wherein   
     
     
        the opening includes a well..Iaddend..Iadd.59.  The method of claim 58 wherein the well is less than 1 μm in diameter..Iaddend..Iadd.60. The method of claim 58 wherein the well is between 0.40 μm and 0.7 μm in diameter..Iaddend..Iadd.61. The method of claim 58 wherein the mask is less than 0.15 μm in diameter..Iaddend..Iadd.62. The method of claim 49 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.63. The method of claim 49 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.64. A method for fabricating a submicron structure on a semiconductor substrate having an oxide layer over the semiconductor substrate and a polysilicon layer over the oxide layer, comprising: depositing a first layer on top of the polysilicon layer;   forming an opening in the first layer;   depositing a non-conformal material over the first layer to form a void in the trench;   removing the non-conformal material down to a top surface of the first layer to expose the void;   depositing a conformal mask material over the first layer and void;   removing the conformal mask material above the first layer; and   etching the first layer and non-conformal material..Iaddend..Iadd.65. The method of claim 64 wherein the first layer is a mask oxide..Iaddend..Iadd.66. The method of claim 64 wherein the non-conformal material is selected from the group consisting of silicon oxide and   
     
     
        silicon nitride..Iaddend..Iadd.67.  The method of claim 64 wherein depositing the non-conformal material includes deposition to a thickness of between 0.3 and 0.45 μm..Iaddend..Iadd.68. The method of claim 64 wherein the conformal mask material is polysilicon..Iaddend..Iadd.69. The method of claim 64 wherein removing the non-conformal mask material down to the top surface of the first layer includes chemical mechanical polishing..Iaddend..Iadd.70. The method of claim 64 wherein removing the conformal mask material above the first layer includes chemical mechanical polishing..Iaddend..Iadd.71. The method of claim 64 wherein etching the first layer and non-conformal material includes an anisotropic etch..Iaddend..Iadd.72. The method of claim 64 wherein etching the first layer and non-conformal material includes an isotropic etch..Iaddend.