Semiconductor integrated circuit

Abstract

Provided on the periphery of a semiconductor chip are a clock input pad 10 and a clock driver 11. Clock pulse generators 13A to 13G are provided to functional blocks 12A to 12F. A clock signal line 14, through which clock signals are transmitted to the clock pulse generators 13A to 13G, is composed of a first clock line 14a extending from the clock driver 14 to the center of the semiconductor chip, and a plurality of second clock lines branching, at the center of the semiconductor chip, from the leading end of the first clock line to extend to the clock pulse generators 13A to 13G respectively.

The invention claimed is: 
     
       1. A semiconductor integrated circuit comprising a plurality of functional blocks provided on a semiconductor chip and a multi-level metal interconnect-wiring layer, wherein: particular one of said plurality of metal interconnect-wiring layers is for the exclusive use of a power supply line which delivers power to said plurality of functional blocks and a clock signal line through which a clock signal is transmitted to said plurality of functional blocks, and   the minimum width of the lines on said particular metal interconnect-wiring layer is greater than the . .maximum.!. .Iadd.minimum .Iaddend.width of lines on the remaining metal interconnect-wiring layers.Iadd., said minimum width of the lines on said particular metal interconnect-wiring layer determined by a first design rule, said minimum width of lines on said remaining metal interconnect-wiring layers determined by a second design rule.Iaddend..   
     
     
       2. A semiconductor integrated circuit as in claim 1, wherein said particular metal interconnect-wiring layer is an uppermost-level layer in the semiconductor chip. 
     
     
       3. A semiconductor integrated circuit as in claim 2, wherein said particular metal interconnect-wiring layer is provided with no interconnect-wirings except for said power supply line and said clock signal line.