Read circuit for accessing dynamic random access memories (DRAMs)

Abstract

DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from output buffer logic utilized in reading data out of the DRAM. Output signals from the level translator stage are applied to a pull up output transistor in an output driver stage, and output signals from the enable gate are connected to a pull down output transistor in the output driver stage. A feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enable gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off. Not only does this novel operation completely eliminate crossing or crossover currents in the output driver stage, but it also introduces minimum time delays in logic swings at the output node of the output driver stage.

We claim: 
     
       1. A system for eliminating crossing currents and minimizing switching delays in a dynamic random access memory operation wherein two logic paths are operative with a given logic swing, a level translating stage is connected in a first logic path and to a pull up output driver transistor in an output driver stage, and a parallel signal processing path is connected as a second logic path and an input of a pull down output transistor in said output driver stage, characterized by: means connected between said level translating stage and said parallel signal processing path for enabling the operation of said parallel signal processing path by an output signal from said level translating stage to thereby ensure that said pull down output transistor is turned on immediately after said pull up output transistor turns off, but not before; said enabling means includes an enable gate having one input connected in said second logic path and another input connected to an output of said level translating stage to thereby generate an enabling output signal applied to said pull down output transistor only after said pull up output transistor turns off; and   one output line from a level translating stage is connected through an inverter to said pull up output transistor and another output line from said level translating stage is connected through an inverter and then through a logic gate where an inverted signal is combined with an input signal to said level translating stage, and an output line from said logic gate is connected as one input to said enable gate, whereby an output signal from said enable gate may be inverted and applied to said pull down output transistor.   
     
     
       2. Access circuitry for driving serially connected pull up and pull down output transistors to generate an output logic swung which has been up converted from a smaller input logic swing, including, in combination: a) a level translator stage connected to receive a small pull up logic swing and operative to convert it to a larger output logic swing;   b) applying means connected between said level translator stage and said pull up output transistor for applying an output logic swing to said pull up output transistor;   c) an enable gate connected between said level translator stage and said pull down output transistor, whereby said enable gage is operative to turn on said pull down output transistor only after a logic swing output from said level translator stage changes levels to thereby turn off said pull up output transistor, thereby eliminating crossing current in the series circuit output connection containing said pull up and pull down output transistors;   d) said level translator stage and said enable gate are connected, respectively, in parallel signal processing paths of a read data processing channel for a DRAM; and   e) one output line from said level translator stage is connected through the applying means to said pull up output transistor and another output line from said level translator stage is connected through an inverter and then through a logic gate where an inverted signal is combined with an input signal to said level translator stage, and an output line from said logic gate is connected as one input to said enable gate, whereby an output signal from said enable gate may be inverted and applied to said pull down output transistor.   
     
     
       3. A dynamic random access memory device having an output buffer electrically coupled to an output driver, said output buffer having an output node, comprising: a) a control latch device, being part of the output buffer, for receiving output buffer input signals and for generating a first output signal at a first output node, said first output signal for sending a pull up signal to the output driver via a level translator device, said pull up signal driving a first potential to said output node of said output buffer, and for generating a second output signal at a second output node, said second output signal for sending a pull down signal to the output driver via a first logic device, said pull down signal driving a second potential to said output node of said output buffer, said first and said second output signals generated in response to said output buffer input signals; and   b) an enabling device, electrically coupled at an input node to an output node of the level translator and electrically coupled from an output node to an input node of the first logic device, said enabling device enabling the pull down signal to reach the output driver only after the pull up signal has been discontinued from the output driver.   
     
     
       4. A dynamic random access memory device, comprising: a) an output driver, having a pull-up circuit, a pull-down circuit, and an output node;   b) an output buffer for accepting a pull-up condition and a pull-down condition, said output buffer electrically coupled to the output driver;   c) a level translator located in the output buffer and responding to the pull-up and pull down conditions to generate a level translator signal at a level translator output node, said level translator signal coupled to said pull-up circuit; and   d) a timing device located in the output buffer and having an input node coupled to said level translator output node and having a first output node electrically coupled to the pull-up circuit and having a second output node electrically coupled to the pull-down circuit, said timing device responding to said level translator signal to generate a first timing signal at said first output node to deactivate said pull-up circuit thereby terminating a driving of a first potential to said output node of said output driver and responding to said level translator signal to generate a second timing signal at said second output node to activate said pull-down circuit thereby driving said output node of said output driver to a second potential, said timing device timing a generation of said first and said second timing signals such that said pull-up circuit is deactivated prior to said pull-down circuit being activated.   
     
     
       5. A dynamic random access memory device, comprising: a) an output driver having a pull-up device, a pull-down device, and an output node interposed between said pull-up device and said pull-down device, a first potential driven to said output node through said pull-up device in response to an active pull-up signal on a control input of said pull-up device and in response to an inactive pull-down signal on a control input of said pull-down device, a second potential driven to said output node through said pull-down device in response to an inactive pull-up signal on said control input of said pull-up device and in response to an active pull-down signal on said control input of said pull-down device;   b) a control circuit in electrical communication with said output device circuit, wherein said control circuit generates said active and inactive pull-up control signals and generates said active and inactive pull-down signals, said control circuit accepting a first data signal at a first input and a second data signal at a second input; and   c) a level translator circuit, an output of said level translator circuit in electrical communication with a third input of said control circuit, said level translator circuit accepting said first data signal and generating a level translated signal to said control circuit at said third input, wherein said active pull-up signal is generated in said control circuit in response to a said first data signal having a first logic state and in response to said level translated signal, and wherein said inactive pull-down signal is generated in said control circuit in response to said second data signal having a second logic state, and wherein said inactive pull-up signal is generated in said control circuit in response to said first data signal having a second logic state and in response to said level translated signal and wherein said active pull-down signal is generated in said control circuit in response to said first data signal having said second logic state, in response to said level translated signal and in response to said second data signal having said first logic state, said control circuit controlling a timing of the generation of said inactive pull-up signal and said active pull-down signal such that said active pull-up signal becomes inactive before said inactive pull-down signal becomes fully active.   
     
     
       6. The dynamic random access memory device of claim 4, wherein said pull-up condition comprises a first signal and a second signal said first and said second signals capable of having first and second logic states, and wherein said pull-down condition comprises a third signal and a fourth signal said third and said fourth signals capable of having said first and second logic states. 
     
     
       7. The dynamic random access memory device of claim 6, where the timing device comprises: a) an inverter coupled to the output from the level translator output node and generating an inverter output signal;   b) a first logic device receiving said inverter output signal at a first input node and receiving one of said signals of said pull-up condition and said pull-down condition at a second input node, said first logic device generating a first logic signal in response to said pull-up condition to control the activation of said pull-up circuit and generating a second logic signal in response to said pull-down condition and said translator signal to control a deactivation of said pull-up circuit; and   c) a second logic device for receiving an output of said first logic device and one of said signals of said pull-up and pull-down conditions, said second logic device generating a third logic signal in response to said pull-up condition to control the deactivation of said pull-down circuit and generating a fourth logic signal in response to said second logic signal and said pull-down condition to control the activation of said pull-down circuit. .Iadd.   
     
     
       8.  A system for minimizing switching delays in a memory device outputting a data signal and its compliment signal through first and second respective logic paths, the first logic path including a level translating stage for receiving the data signal and selectively activating a pull up output driver transistor in response thereto, the second logic path including a pull down output driver transistor, the system comprising: an enable gate for receiving the compliment signal through the second logic path and being enabled in response thereto to selectively activate the pull down output driver transistor, the enable gate being adapted to receive a control signal directing it to activate the pull down output driver transistor if enabled; and   an inverter and a logic gate coupled in combination between the level translating stage and the enable gate for providing the control signal to the enable gate in response to the level translating stage de-activating the pull up output driver transistor. .Iaddend..Iadd.9. Access circuitry in a memory device for driving pull up and pull down output transistors to generate an output logic swing from an input logic swing, the access circuitry comprising:   a level translator stage for receiving a pull up portion of the input logic swing and converting it to a pull up portion of the output logic swing;   an applying circuit coupled to the level translator stage for applying the pull up portion of the output logic swing to the pull up output transistor to selectively activate the pull up output transistor;   an enable gate coupled to the level translator stage for activating the pull down output transistor only after a pull down portion of the input logic swing enables the enable gate and in response to a control signal; and   an inverter and a logic gate coupled in combination between the level translator stage and the enable gate for providing the control signal thereto in response to the level translator stage outputting a pull up portion of an output logic swing that de-activates the pull up output transistor. .Iaddend..Iadd.10. A memory device having an output buffer electrically coupled to an output driver, said output buffer having an output node, the memory device comprising:   a control latch device included in the output buffer for receiving output buffer input signals and for generating first and second complimentary output signals in response;   a level translator device coupled to the control latch device for receiving the first output signal and generating a pull up signal in response thereto to drive a first potential to said output node of said output buffer;   a logic device coupled to the control latch device for receiving the second output signal and generating a pull down signal in response thereto when enabled to drive a second potential to said output node of said output buffer; and   an enabling device coupled to the level translator device, the control latch device, and the logic device for enabling the pull down signal to reach the output driver only after the pull up signal has been   
     
     
        discontinued from the output driver. .Iaddend..Iadd.11.  The memory device of claim 10 wherein the enabling device comprises a NOR gate. .Iaddend..Iadd.12. The memory device of claim 10 wherein the logic device comprises a NAND gate. .Iaddend..Iadd.13. The memory device of claim 10 further comprising a CMOS driver inverter interposed between the level translator device and the output buffer's output node. .Iaddend..Iadd.14. The memory device of claim 10 wherein the output driver includes a pull up transistor and a pull down transistor. .Iaddend..Iadd.15. A memory device comprising: an output driver having a pull-up circuit, a pull-down circuit, and an output node;   an output buffer for accepting a pull-up condition and a pull-down condition, said output buffer coupled to the output driver;   a level translator located in the output buffer and responsive to the pull-up and pull down conditions to generate a level translator signal for said pull-up circuit; and   a timing device located in the output buffer and coupled to said level translator, the pull-up circuit, and the pull-down circuit, said timing device responsive to said level translator signal to generate first and second timing signals, said first timing signal for deactivating said pull-up circuit to terminate a driving of a first potential to said output node, said second timing signal for activating said pull-down circuit to drive said output node to a second potential, said timing device adapted to time its generation of said first and said second timing signals such that said pull-up circuit is substantially deactivated prior to said pull-down circuit being activated. .Iaddend..Iadd.16. The memory device of claim 15, wherein the timing device comprises:   an inverter coupled to the level translator for receiving said level translator signal and generating an inverter output signal in response thereto;   a first logic device for receiving said inverter output signal and responsive to said pull-up condition and said pull-down condition to generate a first logic signal in response to said pull-up condition to control the activation of said pull-up circuit and to generate a second logic signal in response to said pull-down condition and said translator signal to control a deactivation of said pull-up circuit; and   a second logic device for receiving said second logic signal from said first logic device and responsive to one of said pull-up and pull-down conditions to generate a third logic signal in response to said pull-up condition to control the de-activation of said pull-down circuit and to generate a fourth logic signal in response to said second logic signal and said pull-down condition to control the activation of said pull-down circuit. .Iaddend..Iadd.17. A memory device comprising:   an output driver having a pull-up device, a pull-down device, and an output node interposed therebetween, said output driver being adapted to drive a first potential to said output node through said pull-up device in response to an active pull-up control signal and an inactive pull-down control signal, said output driver also being adapted to drive a second potential to said output node through said pull-down device in response to an inactive pull-up control signal and an active pull-down control signal;   a control circuit in electrical communication with said output driver, said control circuit for generating said control signals in response to first and second data signals and a level translated signal such that one of said pull-up and pull down devices is substantially inactive when the other is active; and   a level translator circuit in electrical communication with said control circuit for providing said level translated signal in response to said first data signal. .Iaddend..Iadd.18. A circuit in an output buffer for activating a first output driver switch only after a second output driver switch is substantially de-activated, the second output driver switch being activated through a first inverter by a level translating stage in response to a data signal received by the level translating stage, the circuit comprising:   an enable gate for activating the first output driver switch in response to an activation signal after being enabled by a compliment signal, the compliment signal being the compliment of the data signal; and   a second inverter and a logic gate coupled in combination between the level translating stage and the enable gate for providing the activation signal thereto in response to the level translating stage de-activating the   
     
     
        second output driver switch. .Iaddend..Iadd.19.  The circuit of claim 18 wherein the enable gate comprises a NAND gate and the logic gate comprises a NOR gate. .Iaddend..Iadd.20. An output buffer for outputting an output signal in response to a data signal and its compliment signal, the output buffer comprising: a pull-up output driver switch for selectively outputting the output signal equal to a supply voltage;   a pull-down output driver switch for selectively outputting the output signal equal to a reference voltage;   a level translating stage and a first inverter coupled in combination to the pull-up output driver switch for activating and de-activating the pull-up output driver switch in response to the data signal;   an enable gate coupled to the pull-down output driver switch for activating the pull-down output driver switch in response to an activation signal after being enabled by the compliment signal; and   a second inverter and a logic gate coupled in combination between the level translating stage and the enable gate for providing the activation signal thereto in response to the level translating stage de-activating the pull-up output driver switch. .Iaddend..Iadd.21. The output buffer of claim 20 wherein the output driver switches comprise MOS transistors, wherein the first inverter comprises a CMOS inverter, wherein the enable gate comprises a NAND gate, and wherein the logic gate comprises a NOR   
     
     
        gate. .Iaddend..Iadd.22.  The output buffer of claim 20 further comprising a control latch coupled to the level translating stage and the enable gate for providing the data and compliment signals thereto, respectively. .Iaddend..Iadd.23. A memory device comprising: a memory array; and   access circuitry coupled to the memory array for accessing the memory array, the access circuitry including an output buffer for outputting an output signal in response to a data signal and its compliment signal, the output buffer comprising: a pull-up output driver switch for selectively outputting the output signal equal to a supply voltage;   a pull-down output driver switch for selectively outputting the output signal equal to a reference voltage;   a level translating stage and a first inverter coupled in combination to the pull-up output driver switch for activating and de-activating the pull-up output driver switch in response to the data signal;   an enable gate coupled to the pull-down output driver switch for activating the pull-down output driver switch in response to an activation signal after being enabled by the compliment signal; and   a second inverter and a logic gate coupled in combination between the level translating stage and the enable gate for providing the activation signal thereto in response to the level translating stage de-activating the pull-up output driver switch. .Iaddend..Iadd.24. The memory device of claim 23 wherein the output driver switches comprise MOS transistors, wherein the first inverter comprises a CMOS inverter, wherein the enable gate comprises a NAND gate, and wherein the logic gate comprises a NOR gate. .Iaddend..Iadd.25. The memory device of claim 23 wherein the output buffer further comprises a control latch coupled to the level translating stage and the enable gate for providing the data and compliment signals thereto, respectively. .Iaddend..Iadd.26. A method in an output buffer for activating a first output driver switch only after a second output driver switch is substantially de-activated, the second output driver switch being activated by a level translating stage in response to an active data signal received by the level translating stage, the method comprising:     receiving an active compliment signal, the compliment signal being the compliment of the data signal;   in response to the active compliment signal, enabling the first output driver switch to be activated by an activation signal; and   providing the activation signal in response to the level translating stage de-activating the second output driver switch. .Iaddend.