Simultaneous read and refresh of different rows in a DRAM

Abstract

A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.

I claim: 
     
       1. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising: two or more rows and two or more columns of memory cells;   a write column line corresponding to each column of memory cells;   a read column line corresponding to each column of memory cells;   first and second write row lines corresponding to each row of memory cells;   a read row line corresponding to each row of memory cells;   each memory cell in the array being coupled to the respective write column line, read column line, and read a row line;   each row of memory cells being arranged into a top half-row of memory cells corresponding to each odd-numbered column of memory cells, and a bottom half-row of memory cells corresponding to each even-numbered column of memory cells;   each memory cell in the top half-row being coupled to the respective first write row line;   each memory cell in the bottom half-row being coupled to the respective second write row line;   charge sensing means coupled to each successive pair of write column lines; and   current/voltage sensing means coupled to each read column line.   
     
     
       2. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising: M rows and N columns of memory cells, wherein M and N are integers greater than 1;   a write column line corresponding to each column;   a read column line corresponding to each column;   first and second write row lines corresponding to each row;   a read row line corresponding to each row;   each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;   each memory cell in the top half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective first write row line, and a read row node coupled to the respective read row line;   each memory cell in the bottom half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective second write row line, and a read row node coupled to the respective read row line;   a row of N/2 charge sensing amplifiers having a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column; and   a row of N current/voltage sensing amplifiers having an input coupled to one of the read column lines and an output for providing a digital signal.   
     
     
       3. A memory array configuration as in claim 2 in which each of the memory cells comprises a non-destructive read memory cell. 
     
     
       4. A memory array configuration as in claim 2 in which at least one of the charge sensing amplifier comprises means coupled to a strobe input for selectively enabling and disabling the amplification of the charge sensing amplifier. 
     
     
       5. A memory array configuration as in claim 2 in which at least one of the charge sensing amplifiers comprises: first and second transistors of a first type each having a source, a drain, and a gate, the sources being coupled together and to a first source of supply voltage; and   third and fourth transistors of a second type each having a source, a drain, and a gate, the sources being coupled together and to a second source of supply voltage,   wherein the drains of the first and third transistors and the gates of the second and fourth transistors are coupled together to form the first input, and   the drains of the second and fourth transistors and the gates of the first and third transistors are coupled together to form the second input.   
     
     
       6. A memory array configuration as in claim 5 comprising: means for selectively coupling the coupled sources of the first and second transistors to the first source of supply voltage responsive to an inverted strobe signal; and   means for selectively coupling the coupled sources of the third and fourth transistors to the second source of supply voltage responsive to a strobe signal.   
     
     
       7. A memory array configuration as in claim 2 in which at least one of the current/voltage amplifiers comprises: a differential load having first and second nodes; and   first and second transistors each having a source, a drain, and a gate, the sources being coupled together and to a source of bias current,   wherein the drains of the first and second transistors are respectively coupled to the first and second nodes of the differential load, and   the gate of the first transistor forms the input, the drain of the second transistor forms the output, and the gate of the second transistor is coupled to a reference voltage source.   
     
     
       8. In a memory array including two or more rows and two or more columns of memory cells, a write column line corresponding to each column, a read column line corresponding to each column, and a read row line corresponding to each row, wherein each memory cell in the array is coupled to the respective write column line, read column line, and read row line, a method for allowing simultaneous read and refresh of different rows in the array, the method comprising the steps of: providing first and second write row lines;   arranging each row into a top half-row of memory cells corresponding to each odd-numbered column and a bottom half-row of memory cells corresponding to each even-numbered column;   coupling each memory cell in the top half-row to the respective first write row line;   coupling each memory cell in the bottom half-row to the respective second write row line;   charge sensing each successive pair of write column lines; and   current/voltage sensing each read column line;   read-selecting an entire row of memory cells;   reading data out of the memory cells in the read-selected row;   normalizing each of the write column lines to a reference level;   write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row in order to refresh the write-selected half-row; and   forcing complementary valid logic on successive pairs of write column lines responsive to the charge difference in the write column lines.   
     
     
       9. In a memory array having M rows and N columns of memory cells, wherein M and N are integers greater than 1, a write column line corresponding to each column, a read column line corresponding to each column, a write row line corresponding to each row, a read row line corresponding to each row, a method for allowing simultaneous read and refresh of the memory cells, the method comprising; providing a second write row line for each row of memory cells;   arranging each row into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;   coupling a write row node of each memory cell in the top half-row to a respective first write row line;   coupling a write row node of each memory cell in the bottom half-row to the respective second write row line;   coupling a write column line, a read column line, and a read row line of each memory cell in each row to the respective column and row line;   providing a row of N/2 charge sensing amplifiers having first and second inputs;   coupling the first input of each of the charge sensing amplifiers to an odd-numbered write column line and the second input of each of the charge sensing amplifiers coupled to a next even-numbered write column;   providing a row of N current/voltage sensing amplifiers having an input and an output;   coupling the input of each of the current/voltage sensing amplifiers to one of the read column lines;   providing a digital signal at the output of each of the current/voltage sensing amplifiers;   read-selecting one of the entire rows of memory cells;   reading data out at the output of the current/voltage sensing amplifiers respectively coupled to a read column node of each of the memory cells;   normalizing each of the write column lines to a reference level;   write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row to share stored charge in the memory cell with a corresponding write column line to refresh the write-selected half-row; and   forcing complementary valid levels on successive pairs of write column lines responsive to the charge difference in the write column lines.   
     
     
       10. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 9 in which the step of read-selecting one of the half-rows of memory cells comprises the steps of: coupling the read row line to a logic low; and   simultaneously maintaining the write row line at a logic low.   
     
     
       11. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 9 in which the step of write-selecting another of the half-rows of memory cells comprises the step of coupling the write row line to a logic high. 
     
     
       12. A method for allowing simultaneous reading and refresh of memory cells in a memory as in claim 9 in which the step of forcing complementary valid logic levels on successive pairs of write column lines comprises the step of enabling amplification in the charge sensing amplifiers with a strobe signal. .Iadd. 
     
     
       13.  A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising: at least two rows and at least two columns of memory cells;   a write column line for each column of memory cells;   a read column line for each column of memory cells;   first and second write row lines for each row of memory cells;   a read row line for each row of memory cells;   each memory cell in the array being coupled to an associated write column line, read column line, and read row line;   each row of memory cells being arranged into a first set of memory cells corresponding to a first set of columns of memory cells, and a second set of memory cells corresponding to a second set of columns of memory cells;   the first write row line of each row being coupled to each memory cell in the first set of memory cells of the row;   the second write row line of each row being coupled to each memory cell in the second set of memory cells of the row;   at least one charge sensing device coupled to a write column line of the first column set and a write column line of the second column set; and   a current/voltage sensing device coupled to each read column line..Iaddend..Iadd.14. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:   M rows and N columns of memory cells, wherein M and N are integers greater than 1;   a write column line for each memory cell column;   a read column line for each memory cell column;   first and second write row lines for each memory cell row;   a read row line for each memory cell row;   each row being arranged into a first set of N/2 memory cells corresponding to a first set of columns and a second set of N/2 memory cells corresponding to a second set of columns;   each memory cell in a first set of cells having a write column node coupled to an associated write column line, a read column node coupled to an associated read column line, a write row node coupled to an associated first write row line, and a read row node coupled to an associated read row line;   each memory cell in a second set of cells having a write column node coupled to an associated write column line, a read column node coupled to an associated read column line, a write row node coupled to an associated second write row line, and a read row node coupled to an associated read row line;   a group of N/2 charge sensing amplifiers each having a first input coupled to a write column line of the first column set and second input coupled to a write column line of the second column set; and   a group of N current/voltage sensing amplifiers each having an input coupled to a read column line and an output for providing a digital signal..Iaddend..Iadd.15. A memory array configuration as in claim 14 in which each of the memory cells comprises a non-destructive read memory   
     
     
        cell..Iaddend..Iadd.16.  A memory array configuration as in claim 14 in which at least one of the charge sensing amplifiers is coupled to a strobe input for selectively enabling and disabling the amplification of that charge sensing amplifier..Iaddend..Iadd.17. A memory array configuration as in claim 14 in which at least one of the charge sensing amplifiers comprises: first and second transistors of a first type each having a source, a drain, and a gate, the sources being coupled together and to a first source of supply voltage; and   third and fourth transistors of a second type each having a source, a drain, and a gate, the sources being coupled together and to a second source of supply voltage,   wherein the drains of the first and third transistors and the gates of the second and fourth transistors are coupled together to form the first input, and   the drains of the second and fourth transistors and the gates of the first and third transistors are coupled together to form the second input..Iaddend..Iadd.18. A memory array configuration as in claim 17 comprising:   means for selectively coupling the coupled sources of the first and second transistors to the first source of supply voltage responsive to an inverted strobe signal; and   means for selectively coupling the coupled sources of the third and fourth transistors to the second source of supply voltage responsive to a strobe   
     
     
        signal..Iaddend..Iadd.19.  A memory array configuration as in claim 14 in which at least one of the current/voltage amplifiers comprises: a differential load having first and second nodes; and   first and second transistors each having a source, a drain, and a gate, the sources being coupled together and to a source of bias current,   wherein the drains of the first and second transistors are respectively coupled to the first and second nodes of the differential load, and   the gate of the first transistor forms the input, the drain of the second transistor forms the output, and the gate of the second transistor is   
     
     
        coupled to a reference voltage source..Iaddend..Iadd.20.  In a memory array including at least two rows and at least two columns of memory cells, a write column line corresponding to each column, a read column line corresponding to each column, and a read row line corresponding to each row, wherein each memory cell in the array is coupled to its respective write column line, read column line, and read row line, a method for allowing simultaneous read and refresh of cells of different rows in the array, the method comprising the steps of: providing first and second write row lines for each row;   arranging each row into a first set of memory cells corresponding to a first set of columns and a second set of memory cells corresponding to a second set of columns;   coupling the first write row line for each row to each memory cell in the first set of memory cells for the row;   coupling the second write row line for each row to each memory cell in the second set of memory cells for the row;   charge sensing paired write column lines, one from each of the first and second sets of columns;   current/voltage sensing each read column line;   read-selecting an entire row of memory cells;   reading data out of the memory cells in the read-selected row;   normalizing each of the write column lines to a reference level;   write-selecting, substantially simultaneously with the step of read-selecting, the first or second set of memory cells from a row different than the read-selected row in order to refresh the write-selected set of memory cells; and   forcing complementary valid logic on the paired write column lines responsive to the charge difference in the write column lines of the pair..Iaddend..Iadd.21. In a memory array having M rows and N columns of memory cells, wherein M and N are integers greater than 1, a write column line corresponding to each column, a read column line corresponding to each column, a write row line corresponding to each row, a read row line corresponding to each row, a method for allowing simultaneous read and refresh of first and second groups of memory cells, the method comprising:   providing a second write row line for each row of memory cells;   arranging each cell row into a first set of N/2 memory cells corresponding to a first set of columns and a second set of N/2 memory cells corresponding to a second set of columns;   coupling a write row node of each memory cell in a first set of cells to a first write row line for that row;   coupling a write row node of each memory cell in a second set of cells to a second write row line for that row;   coupling a write column node, a read column node, and a read row node of each memory cell in each row to its associated respective write column line, read column line and read row line;   providing a group of N/2 charge sensing amplifiers having first and second inputs;   coupling the first input of each of the charge sensing amplifiers to a write column line of the first column set and the second input of each of the charge sensing amplifiers to a write column line of the second column set;   providing a group of N current/voltage sensing amplifiers having an input and an output;   coupling the input of each of the current/voltage sensing amplifiers to one of the read column lines;   read-selecting one of the entire rows of memory cells;   reading data out at the output of the current/voltage sensing amplifiers;   normalizing each of the write column lines to a reference level;   write-selecting, simultaneously with the step of read-selecting, a first set or a second set of memory cells from a row different than the read-selected row to share stored charge in the memory cell with a corresponding write column line to refresh the write-selected set; and   forcing complementary valid levels on the paired write column lines responsive to the charge difference in the write column   
     
     
        lines..Iaddend..Iadd.22.  A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 21 in which read-selecting one of the sets of memory cells comprises the steps of: coupling the read row line to a logic low; and   simultaneously maintaining the write row line at a logic low..Iaddend..Iadd.23. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 21 in which write-selecting another of the sets of memory cells comprises coupling the write row line to a logic high..Iaddend..Iadd.24. A method for allowing simultaneous reading and refresh of memory cells in a memory as in claim 21 in which forcing complementary valid logic levels on paired write column lines comprises the step of enabling amplification in the charge   
     
     
        sensing amplifiers with a strobe signal..Iaddend..Iadd.25.  A memory cell array configuration providing the capability for simultaneous respective read and refresh of a first group and a second group of memory cells in the array, comprising: at least two rows and at least two columns of cells, each row comprising a first set and a second set of cells;   a read column line for each column of cells;   a write column line for each column of cells;   a read row line for each row of cells; and   a first write row line for a first cell set of each row and a second write row line for a second cell set of each row..Iaddend..Iadd.26. A memory cell array configuration providing the capability of simultaneous, respective read and refresh of first and second groups of memory cells in the array located on respective first and second selected rows of the array, the configuration comprising:   at least two rows and at least two columns of memory cells;   a charge sensing circuit associated with each column of memory cells for sensing charge stored in the memory cells of the associated column;   a current source associated with each column of memory cells; and   a current/voltage sensing circuit associated with each column of memory cells for sensing any current flow through the current source associated with the column indicative of charge stored in the memory cells of the   
     
     
        column..Iaddend..Iadd.27.  The memory cell array configuration of claim 26, wherein each charge sensing circuit is coupled to two different columns of memory cells..Iaddend..Iadd.28. The memory cell array configuration of claim 26, including one current/voltage sensing circuit for each column of memory cells in the array..Iaddend..Iadd.29. A memory cell array configuration for cell refresh, comprising: at least one row of memory cells having a write row line associated therewith;   at least two columns of memory cells, each column having a write column line and a read column line associated therewith; and   a charge sensing circuit communicable with write column lines of first and second columns of said at least two columns for sensing charge stored in memory cells of the first and second columns..Iaddend..Iadd.30. A multi-row, multi-column memory array configured for simultaneous access to two memory cells in the same column, comprising:   at least two rows and at least two columns of dual-port memory cells;   a write column line and a read column line for each cell column;   at least one write row line and a read row line for each cell row;   each cell being coupled to a write column line, a read column line, a write row line and a read row line;   charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and   a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in   
     
     
        memory cells coupled to the read column line..Iaddend..Iadd.31.  A multi-row, multi-column memory array configured for simultaneous reading of two memory cells in the same column, comprising: at least two rows and at least two columns of dual-port memory cells;   a write column line and a read column line for each cell column;   at least one write row line and a read row line for each cell row;   each cell being coupled to a write column line, a read column line, a write row line and a read row line;   charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and   a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in memory cells coupled to the read column line..Iaddend..Iadd.32. A multi-row, multi-column memory array of dual-port memory cells configured for reading of cells through either port, comprising:   at least two rows and at least two columns of dual-port memory cells;   a write column line and a read column line for each cell column;   at least one write row line and a read row line for each cell row;   each cell being coupled to a write column line, a read column line, a write row line and a read row line;   charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and   a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in   
     
     
        memory cells coupled to the read column line..Iaddend..Iadd.33.  A multi-row, multi-column memory array of dual-port memory cells configured for reading of each cell, comprising: at least two rows and at least two columns of dual-port memory cells;   a write column line and a read column line for each cell column;   at least one write row line and a read row line for each cell row;   each cell being coupled to a write column line, a read column line, a write row line and a read row line;   charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and   a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in memory cells coupled to the read column line..Iaddend.