Semiconductor memory device

Abstract

A semiconductor memory device is provided having a read out gate for detecting and providing to a main I/O line pair the potential difference of a sub-data input/output line pair, and a write gate for transferring data of the main I/O line pair to the sub-data input/output line pair in an energy region surrounded by a sense amplifier region and a word line coupling region. By providing the read out gate and the write gate in the empty region which was not conventionally used, the access operation can be carried out at high speed without increasing the chip area of the semiconductor memory device.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a plurality of memory cell regions provided in row and column directions,   a main data input/output line pair for transmitting externally generated data and internally generated data,   a sub-data input/output line pair provided in a region between a pair of memory cell regions in said column direction for transmitting data to an adjacent memory cell region in said column direction,   a plurality of data input/output control means provided in the region between the pair of memory cell regions in said column direction for carrying out data input/output control between each bit line pair of an adjacent memory cell in said column direction and said sub-data input/output line pair,   a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of a word line,   a plurality of read out means provided in a region surrounded by the region in which said data input/output control means are provided and by a region in which said impedance reducing means are provided for detecting and providing to said main data input/output line pair the potential difference of said sub-data input/output line pair, and   writing means provided in a region surrounded by the region in which said data input/output control means are provided and by a region in which said impedance reducing means are provided for transferring to said sub-data input/output line pair the data of said main data input/output line pair.   
     
     
       2. The semiconductor memory device according to claim 1, wherein said word line comprises a polysilicon layer formed on a semiconductor substrate and a metal line formed on said polysilicon layer,   said region in which said impedance reducing means is provided comprises a contact hole connecting said metal line and said polysilicon layer by every predetermined distance.   
     
     
       3. The semiconductor memory device according to claim 1, wherein said means for reducing the impedance of said word line comprises buffer means. 
     
     
       4. The semiconductor memory device according to claim 1, wherein said data input/output control means comprises a sense amplifier for detecting the potential difference in each bit line pair of an adjacent memory cell region, and   an input/output gate connected between each bit line pair of said adjacent memory cell region and said sub-data input/output line pair.   
     
     
       5. The semiconductor memory device according to claim 4, wherein said sense amplifier has an area substantially equal to that of said read out means. 
     
     
       6. The semiconductor memory device according to claim 1, wherein said region surrounded by the region in which said data input/output control means are provided and by the region in which said impedance reducing means are provided comprises equalize means for equalizing said sub- o data input/output line pair. 
     
     
       7. The semiconductor memory device according to claim 1, wherein said region surrounded by a region in which said data input/output control means are provided and by a region in which said impedance reducing means are provided further comprises means for limiting the potential difference of signals appearing in a sub-data input/output line pair to a constant potential. 
     
     
       8. A semiconductor memory device comprising: a plurality of memory cell regions arranged in row and column directions, each including a plurality of word lines provided in the row direction, a plurality of bit lines provided in the column direction, and a plurality of memory cells provided at the crossings of each word line and each bit line,   a main data input/output line pair for transmitting externally generated data and internally generated data,   a plurality of sub-data input/output line pairs provided between each pair of memory cell regions of said column direction, each transmitting data with respect to an adjacent memory cell region in said column direction,   a plurality of sense amplifiers for detecting the potential of each bit line pair in said memory cell region of said column direction,   a plurality of input/output gates provided between each pair of memory cell region of said column direction, each being connected between each bit line pair of the adjacent memory cell region in said column direction and said sub-data input/output line pair,   a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of said word line,   a plurality of read out means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by a region in which said impedance reducing means are provided, and   write means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by the region in which said impedance reducing means are provided for transferring data on said main data input/output line pair to said sub-data input/output line pair.   
     
     
       9. The semiconductor memory device according to claim 8, wherein said read out means is activated right after the activation of said amplifier. 
     
     
       10. A semiconductor memory device comprising: a plurality of memory cell regions arranged in row and column directions, each including a plurality of word lines provided in the row direction, a plurality of bit lines provided in the column direction, and a plurality of memory cells provided at crossings of each word line and each bit line,   a main data input/output line pair for transferring externally generated data and internally generated data,   a plurality of sub-data input/output line pairs provided between each pair of memory cell regions of said column direction, each transmitting data with respect to an adjacent memory cell region in said column direction,   a plurality of sense amplifiers for detecting the potentials of each bit line pair of memory cell regions of said column direction,   a plurality of input/output gates provided between each pair of memory cell regions of said column direction, each being connected between each bit line pair of an adjacent memory cell region and said sub-data input/output line pair,   a plurality of impedance reducing means provided between memory cell regions of said row direction for reducing the impedance of said word line,   a plurality of read out means provided in a region surrounded by a region in which said input/output gates and said sense amplifiers are provided and by a region in which said impedance reducing means are provided for detecting and providing to said main data input/output line pair the potential difference of said sub-data input/output line pair,   write means provided in a region surrounded by the region in which said input/output gates and said sense amplifiers are provided and by the region in which said impedance reducing means are provided for transferring data of said main data input/output line pair to said sub-data input/output line pair, and   means for controlling the potential difference of said sub-data input/output line pair to a constant potential. .Iadd.   
     
     
       11.  A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a plurality of rows and columns, said memory cell array being divided into a plurality of groups for every predetermined number of said plurality of columns, each group being further divided into a plurality of blocks for every predetermined number of said plurality of rows, to have a plurality of memory cell blocks,   a plurality of bit line pairs provided in said predetermined number of columns in each of said plurality of memory cell blocks in said memory cell array, each bit line pair being connected to a plurality of memory cells arranged in a corresponding column,   a plurality of sense amplifier blocks provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array, each sense amplifier block including a plurality of sense amplifier means provided in said predetermined number of columns of a corresponding memory cell block, each sense amplifier means detecting and amplifying potential difference appearing on a bit line pair arranged in a corresponding column,   a plurality of sub-data input/output line pairs provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array,   a plurality of transfer gate blocks provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array, each transfer gate block including a plurality of transfer gates provided corresponding to respective ones of said plurality of bit line pairs provided in a corresponding memory cell block, each transfer gate being responsive to a column selecting signal for transmitting data between a corresponding bit line pair and a corresponding sub-data input/output line pair,   a plurality of main data input/output line pairs provided corresponding to respective ones of said plurality of groups divided for every said predetermined number of columns in said memory cell array,   a plurality of read out means provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each read out means being responsive to a block selecting signal for reading for providing potential difference to a corresponding main data input/output line pair according to potential difference appearing on a corresponding sub-data input/output line pair, and   a plurality of writing means provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each writing means being responsive to a block selecting signal for writing for providing potential difference appearing on a corresponding main data input/output line pair to a corresponding sub-data input/output line pair. .Iaddend..Iadd.12. The semiconductor memory device according to claim 11, wherein   each of said plurality of sub-data input/output line pairs is arranged along a row direction,   each of said plurality of main data input/output line pairs is arranged along a column direction. .Iaddend..Iadd.13. The semiconductor memory device according to claim 11, wherein   each memory cell block is divided into two in the column direction with a corresponding sense amplifier block interposed therebetween,   each bit line pair comprises a right side bit line pair connected to a plurality of memory cells arranged at one side of a two-divided memory cell block of a corresponding column, and a left side bit line pair connected to a plurality of memory cells arranged at the other side of the two-divided memory cell block of the corresponding column,   each sense amplifier means comprises a sense amplifier, a pair of right side selecting gates for electrically connecting said sense amplifier to a right side bit line pair arranged in a corresponding column in response to a selecting signal, and a pair of left side selecting gates for electrically connecting said sense amplifier to a left side bit line pair arranged in the corresponding column in response to a selecting signal. .Iaddend..Iadd.14. The semiconductor memory device according to claim 11, wherein each read out means comprises a first MOS transistor receiving said block selecting signal for reading at a gate electrode, a second MOS transistor connected in series with said first MOS transistor between one data input/output line of a corresponding main data input/output line pair and a ground potential node, and having a gate electrode connected to one sub-data input/output line of a corresponding sub-data input/output line pair, a third MOS transistor receiving said block selecting signal for reading at a gate electrode, and a fourth MOS transistor connected in series with said third MOS transistor between the other data input/output line of the corresponding main data input/output line pair and the ground potential node, and having a gate electrode connected to the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.15. The semiconductor memory device according to claim 14, wherein each writing means comprises a fifth MOS transistor receiving said block selecting signal for writing at a sate electrode, and connected between one main data input/output line of a corresponding main data input/output line pair and one sub-data input/output line of a corresponding sub-data input/output line pair, and a sixth MOS transistor receiving said block selecting signal for writing at a gate electrode, and connected between the other main data input/output line of the corresponding main data input/output line pair and the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.16. The semiconductor memory device according to claim 14, further comprising a plurality of equalized circuits provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each equalized circuit including a seventh MOS transistor receiving a first equalize signal at a gate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and an intermediate potential node, an eighth MOS transistor receiving said first equalize signal at a gate electrode, and connected between the other sub-data input/output line of the corresponding sub-data input/output line pair and the intermediate potential node, and a ninth MOS transistor receiving a second equalize signal at a gate electrode, and connected between said one sub-data input/output line and said the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.17. The semiconductor memory device according to claim 14, further comprising a plurality of load circuits provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each load circuit including a tenth MOS transistor receiving a control signal at a gate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and a power supply potential node, and an eleventh MOS transistor receiving said control signal at a sate electrode, and connected between the other sub-data input/output line of the corresponding subdata input/output line pair and the power supply potential node. .Iaddend..Iadd.18. A semiconductor memory device comprising:   a memory cell array having a plurality of groups arranged along a row direction, each group having a plurality of memory cell blocks each including a plurality of memory cells arranged along a column direction,   a plurality of bit line pairs provided in each of said plurality of memory cell blocks in said memory cell array, each bit line pair being connected to a plurality of memory cells arranged in a corresponding column,   a plurality of sense amplifier blocks provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array, each sense amplifier block including a plurality of sense amplifier means each for detecting and amplifying potential difference appearing on a bit line pair arranged in a corresponding column of a corresponding memory cell block,   a plurality of sub-data input/output line pairs provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array,   a plurality of transfer gate blocks provided corresponding to respective ones of said plurality of memory cell blocks in said memory cell array, each transfer gate block including a plurality of transfer gates, each transfer gate being responsive to a column selecting signal for transmitting data between a corresponding bit line pair and a corresponding sub-data input/output line pair,   a plurality of main data input/output line pairs provided corresponding to respective ones of said plurality of groups in said memory cell array,   a plurality of read out means provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each read out means being responsive to a block selecting signal for reading for providing potential difference to a corresponding main data input/output line pair according to potential difference appearing on a corresponding sub-data input/output line pair,   a plurality of writing means provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each writing means being responsive to a block selecting signal for writing for providing potential difference appearing on a corresponding main data input/output line pair to a corresponding sub-data input/output line pair. .Iaddend..Iadd.19. The semiconductor memory device according to claim 18, wherein each read out means comprises a first MOS transistor receiving said block selecting signal for reading at a rate electrode, a second MOS transistor connected in series with said first MOS transistor between one data input/output line of a corresponding main data input/output line pair and a ground potential node, and having a gate electrode connected to one sub-data input/output line of a corresponding sub-data input/output line pair, a third MOS transistor receiving said block selecting signal for reading at a gate electrode, and a fourth MOS transistor connected in series with said third MOS transistor between the other data input/output line of the corresponding main data input/output line pair and the ground potential node, and having a gate electrode connected to the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.20. The semiconductor memory device according to claim 19, wherein each writing means comprises a fifth MOS transistor receiving said block selecting signal for writing at a gate electrode, and connected between one main data input/output line of a corresponding main data input/output line pair and one sub-data input/output line of a corresponding sub-data input/output line pair, and a sixth MOS transistor receiving said block selecting signal for writing at a gate electrode, and connected between the other main data input/output line of the corresponding main data input/output line pair and the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.21. The semiconductor memory device according to claim 19, further comprising a plurality of equalized circuits provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each equalized circuit including a seventh MOS transistor receiving a first equalize signal at a gate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and an intermediate potential node, an eighth MOS transistor receiving said first equalize signal at a gate electrode, and connected between the other sub-data input/output line of the corresponding sub-data input/output line pair and the intermediate potential node, and a ninth MOS transistor receiving a second equalize signal at a gate electrode, and connected between said one sub-data input/output line and said the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.22. The semiconductor memory device according to claim 19, further comprising a plurality of load circuits provided corresponding to respective ones of said plurality of sub-data input/output line pairs, each load circuit including a tenth MOS transistor receiving a control signal at a sate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and a power supply potential node, and an eleventh MOS transistor receiving said control signal at a gate electrode, and connected between the other sub-data input/output line of the corresponding subdata input/output line pair and the power supply potential node. .Iaddend..Iadd.23. A semiconductor memory device comprising:   a semiconductor substrate including at a main surface thereof a plurality of memory cell forming regions arranged in a matrix in a row direction and a column direction, a plurality of sense amplifier forming regions each being arranged between two adjacent memory cell forming regions in the column direction, a plurality of signal routing regions each arranged between two adjacent memory cell forming regions in the row direction, and a plurality of empty regions each arranged between two adjacent sense amplifier forming regions in the row direction,   a plurality of memory cells provided in each memory cell forming region in said semiconductor substrate,   a plurality of bit line pairs provided on each memory cell forming region in said semiconductor substrate, each bit line pair being connected to a corresponding plurality of memory cells,   a plurality of word lines provided on the main surface of said semiconductor substrate, each word line being arranged in a corresponding row provided in the plurality of memory cell forming regions arranged along the row direction,   a plurality of sense amplifier means provided in the plurality of sense amplifier forming regions in said semiconductor substrate, each detecting and amplifying potential difference appearing on a corresponding bit line pair,   a plurality of sub-data input/output line pairs provided on the main surface of said semiconductor substrate, corresponding to respective ones of said plurality of sense amplifier forming regions,   a plurality of transfer gates provided on the main surface of said semiconductor substrate, corresponding to respective ones of said plurality of sense amplifier means, each transfer gate being responsive to a column selecting signal for transmitting data between a bit line pair connected to a corresponding sense amplifier means and a corresponding sub-data input/output line pair,   a plurality of main data input/output line pairs provided on the main surface of said semiconductor substrate, each main data input/output line pair arranged in a plurality of said signal routing regions corresponding to a unit of a plurality of memory cell forming regions arranged in the column direction,   a plurality of read out means provided on a plurality of empty regions in said semiconductor substrate, corresponding to respective ones of said plurality of subdata input/output line pairs, each read out means for reading for providing potential difference to a corresponding main data input/output line pair according to potential difference appearing on a corresponding subdata input/output line pair,   and a plurality of writing means provided on said plurality of empty regions of said semiconductor substrate, corresponding to respective ones of said plurality of sub-data input/output line pairs, each writing means for writing for providing potential difference appearing on a corresponding main data input/output line pair to a corresponding sub-data input/output line pair. .Iaddend..Iadd.24. The semiconductor memory device according to claim 23. wherein   each of said plurality of sub-data input/output line pairs is arranged in a row direction,   each of said plurality of main data input/output line pairs is arranged in a column direction. .Iaddend..Iadd.25. The semiconductor memory device according to claim 23,   a memory cell block being formed of predetermined numbers of memory cells formed in two memory cell forming regions with each sense amplifier forming region interposed therebetween in the column direction,   wherein bit line pairs provided on a memory cell forming region on one side, with respect to the sense amplifier forming region, having one of the predetermined numbers of memory cells of each memory cell block provided being right side bit line pairs, and bit line pairs provided on a memory cell forming region on the other side, with respect to the sense amplifier forming region, having the other of the predetermined numbers of memory cells of each memory cell block provided being left side bit line pairs,   wherein each sense amplifier means provided in each sense amplifier forming region includes a sense amplifier, a pair of right side selecting rates responsive to a selecting signal for electrically connecting said sense amplifier with a right side bit line pair arranged in a corresponding column, and a pair of left side selecting gates responsive to a selecting signal for electrically connecting said sense amplifier with a left side bit line pair arranged in the corresponding column. .Iaddend..Iadd.26. The semiconductor memory device according to claim 25, wherein each read out means comprises a first MOS transistor receiving said block selecting signal for reading at a gate electrode, a second MOS transistor connected in series with said first MOS transistor between one data input/output line of a corresponding main data input/output line pair and a around potential node, and having a sate electrode connected to one sub-data input/output line of a corresponding sub-data input/output line pair, a third MOS transistor receiving said block selecting signal for reading at a gate electrode, and a fourth MOS transistor connected in series pith said third MOS transistor between the other data input/output line of the corresponding main data input/output line pair and the around potential node, and having a gate electrode connected to the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.27. The semiconductor memory device according to claim 26, wherein each writing means comprises a fifth MOS transistor receiving said block selecting signal for writing at a gate electrode, and connected between one main data input/output line of a corresponding main data input/output line pair and one sub-data input/output line of a corresponding sub-data input/output line pair, and a sixth MOS transistor receiving said block selecting signal for writing at a gate electrode, and connected between the other main data input/output line of the corresponding main data input/output line pair and the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.28. The semiconductor memory device according to claim 26, further comprising a plurality of equalized circuits provided on the plurality of empty regions in said semiconductor substrate, corresponding to respective ones of said plurality of sub-data input/output line pairs, each equalized circuit including a seventh MOS transistor receiving a first equalize signal at a gate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and an intermediate potential node, an eighth MOS transistor receiving said first equalize signal at a gate electrode, and connected between the other sub-data input/output line of the corresponding sub-data input/output line pair and the intermediate potential node, and a ninth MOS transistor receiving a second equalize signal at a gate electrode, and connected between said one sub-data input/output line and said the other sub-data input/output line of the corresponding sub-data input/output line pair. .Iaddend..Iadd.29. The semiconductor memory device according to claim 26, further comprising a plurality of load circuits provided on the plurality of empty regions of the semiconductor substrate, corresponding to respective ones of said plurality of sub-data input/output line pairs, each load circuit including a tenth MOS transistor receiving a control signal at a gate electrode, and connected between one sub-data input/output line of a corresponding sub-data input/output line pair and a power supply potential node, and an eleventh MOS transistor receiving said control signal at a gate electrode, and connected between the other sub-data input/output line of the corresponding sub-data input/output line pair and the power supply potential node. .Iaddend..Iadd.30. A semiconductor memory device comprising:   a semiconductor substrate including at a main surface thereof a plurality of memory cell forming regions arranged in a matrix in a row direction and a column direction, a plurality of sense amplifier forming regions each being arranged between two adjacent memory cell forming regions in the column direction, a plurality of space regions each arranged between two adjacent memory cell forming regions in the row direction, and a plurality of empty regions each arranged between two adjacent sense amplifier forming regions in the row direction,   a plurality of memory cells provided in each memory cell forming region in said semiconductor substrate, each memory cell including one MOS transistor and one capacitor,   a plurality of bit line pairs provided on each memory cell forming region in said semiconductor substrate, each bit line pair being connected to one source/drain regions of MOS transistors of a corresponding plurality of memory cells,   a plurality of word lines provided on the main surface of said semiconductor substrate, each word line being integrally formed with gate electrodes of MOS transistors of a plurality of memory cells arranged in a corresponding row provided in the plurality of memory cell forming regions arranged alone the row direction,   a plurality of sense amplifier means provide in the plurality of sense amplifier forming regions in said semiconductor substrate, each detecting and amplifying potential difference appearing on a corresponding bit line pair,   a plurality of sub-data input/output line pairs provided on the main surface of said semiconductor substrate, corresponding to respective ones of said plurality of sense amplifier forming regions,   a plurality of transfer gates provided on the main surface of said semiconductor substrate, corresponding to respective ones of said plurality of sense amplifier means, each transfer gate being responsive to a column selecting signal for transmitting data between a bit line pair connected to a corresponding sense amplifier means and a corresponding sub-data input/output line pair,   a plurality of main data input/output line pairs provided on the main surface of said semiconductor substrate, each main data input/output line pair corresponding to a unit of a plurality of memory cell forming regions arranged in the column direction, and passing a plurality of said space regions arranged alone one side of a corresponding unit of a plurality of memory cell forming region, said one side being perpendicular to the row direction,   a plurality of read out means provided on a plurality of empty regions in said semiconductor substrate, corresponding to respective ones of said plurality of sub-data input/output line pairs, each read out means being responsive to a block electing signal for reading for providing potential difference to a corresponding main data input/output line pair according to potential difference appearing on a corresponding sub-data input/output line pair, and   a plurality of writing means provided on said plurality of empty regions of said semiconductor substrate, corresponding to respective ones of said plurality of sub-data input/output line pairs, each writing means being responsive to a block selecting signal for writing for providing potential difference appearing on a corresponding main data input/output line pair to a corresponding sub-data input/output line pair. .Iaddend.