Surface field effect transistor with depressed source and/or drain areas for ULSI integrated devices

Abstract

A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions. The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide. The modified fabrication steps are readily integrable in a normal CMOS fabrication process.

What we claim is: 
     
       1. A . .surface.!. field effect . .integrated.!. transistor .Iadd.structure, comprising: .Iaddend. . .formed in.!. a semiconducting substrate having a . .surface.!. region.Iadd., near a first surface thereof, .Iaddend.with an electrical conductivity of a first type.Iadd.; .Iaddend.   . .constituting.!. a channel region . .of the transistor.!. .Iadd.within said substrate.Iaddend., . .which.!. .Iadd.said .Iaddend.channel region . .is.!. .Iadd.being .Iaddend.confined from one side by a source region and from an opposite side by a drain region, both .Iadd.said source region and said drain region .Iaddend.having a .Iadd.second .Iaddend.conductivity . .of.!. .Iadd.type .Iaddend.opposite .Iadd.to said first .Iaddend.type.Iadd., and said drain region having a graded diffusion boundary, corresponding to multiple diffusions within said drain region with dopants of said second type, adjacent said channel; .Iaddend.   . .in respect to said channel region and being formed by implanting and diffusing a dopant in the semiconductor through respective drain and source areas of the surface of said semiconducting substrate,.!. said channel region being topped with a gate electrode formed above . .the.!. .Iadd.said .Iaddend.semiconducting substrate and electrically isolated therefrom by a dielectric gate layer. .,.!..Iadd.; .Iaddend.   said source and .Iadd.said .Iaddend.drain regions being electrically contacted through contacts between the semiconducting substrate and a conducting material deposited . .on said respective areas.!. .Iadd.thereon.Iaddend.,   wherein the surface of the semiconducting substrate . .in the area of.!. .Iadd.over .Iaddend.said drain region has a level lower than the level of the surface of the semiconducting substrate in the area of said channel region . .which is topped with.!. .Iadd.under .Iaddend.said dielectric gate layer and said gate electrode, the difference between the levels of the surface of the semiconducting substrate in the gate area and in the drain area being between 50 and 500 nanometers.   
     
     
       2. The transistor according to claim 1, wherein said semiconducting substrate is excavated in said drain area.Iadd., but not in said source area, .Iaddend.to provide said difference between the levels of the surface of the semiconducting substrate in the gate area and . .in the.!. .Iadd.over said .Iaddend.drain . .area.!. .Iadd.region.Iaddend.. 
     
     
       3. The transistor according to claim 1, wherein the surface of the . .semi-conducting.!. .Iadd.semiconducting .Iaddend.substrate is . .similarly.!. lowered .Iadd.not only over said drain region, but .Iaddend.also . .in the.!. .Iadd.over said .Iaddend.source . .area of the transistor beside in the drain area thereof.!. .Iadd.region.Iaddend.. 
     
     
       4. The transistor according to claim 3, wherein spacers in the form of tapered appendices of a dielectric material are present on opposite sides of said gate electrode and of said dielectric gate layer and of . .the.!. .Iadd.a .Iaddend.vertical wall of the semiconducting substrate . .whose surface in the.!. .Iadd.laterally adjoining the surfaces of said .Iaddend.drain and source . .areas confining on opposite sides said gate area.!. .Iadd.regions.Iaddend.; . .is lower than in the gate area the implantation of said dopant for forming.!. said drain and source regions . .taking place through apertures.!. .Iadd.having lateral boundaries at least partially .Iaddend.defined, near . .the.!. .Iadd.said .Iaddend.gate area, by said spacers of dielectric material. 
     
     
       5. The transistor according to claim 4, wherein said drain and source regions .Iadd.each .Iaddend.comprise a first region having a concentration of dopant atoms markedly lower than the concentration of dopant atoms of a second inner region contained within said first region. 
     
     
       6. The transistor of claim 1 wherein said drain region is rounded at its bottom corner. .Iadd.7. The transistor of claim 1, wherein said source and drain regions are mutually symmetrical. .Iaddend..Iadd.8. The transistor of claim 1, wherein said source and drain regions each comprise two different dopant species with different diffusivities. .Iaddend..Iadd.9. An integrated circuit insulated gate field effect transistor structure, comprising: a body of semiconductor material;   source and drain diffusions of a first conductivity type at said first surface of said body, said source and drain regions defining a channel region of a second conductivity type therebetween, said second conductivity type being different from said first conductivity type:   a gate structure overlying said first surface above said channel region, and capacitively coupled to said channel region through a thin gate oxide layer;   wherein said first surface of said body is recessed over said drain region, to a depth of between 50 and 500 nanometers below the level of said first surface under said gate structure;   and wherein said drain comprises two different dopant species of the same   
     
     
        type having different diffusivities. .Iaddend..Iadd.10.  The transistor of claim 9, wherein said source and drain regions are mutually symmetrical. .Iaddend..Iadd.11. The structure of claim 9, wherein said common conductivity type is N-type. .Iaddend..Iadd.12. The structure of claim 9, wherein said semiconductor material comprises silicon, and said source and drain regions each comprise silicide cladding at a respective surface thereof. .Iaddend..Iadd.13. The structure of claim 9, wherein said first surface is radiused near the boundary between said drain region and said channel region. .Iaddend..Iadd.14. The structure of claim 9, wherein said gate structure comprises polycrystalline silicon. .Iaddend..Iadd.15. The structure of claim 9, wherein said gate structure comprises polycrystalline silicon overlaid with silicide cladding at a surface thereof. .Iaddend..Iadd.16. An integrated circuit insulated gate field effect transistor structure, comprising: a body of semiconductor material;   source and drain diffusions of a first conductivity type at said first surface of said body, said source and drain regions defining a channel region of a second conductivity type therebetween, said second conductivity type being different from said first conductivity type;   a gate structure overlying said first surface above said channel region, and capacitively coupled to said channel region through a thin gate oxide layer; said gate structure comprising a dielectric sidewall spacer on the sidewall of said gate structure adjacent to said drain diffusion;   wherein said first surface of said body is recessed over said drain region, to a depth of between 50 and 500 nanometers below the level of said first surface under said gate structure, and wherein said spacer extends down below the rest of said gate structure, to said first surface over said drain diffusion;   wherein said drain has a graded diffusion boundary, corresponding to multiple diffusions with dopants of said second type, adjacent said channel. .Iaddend..Iadd.17. The structure of claim 16, wherein said common conductivity type is N-type. .Iaddend..Iadd.18. The surface of claim 16, wherein said source and drain regions each comprise two different dopant species with different diffusivities. .Iaddend..Iadd.19. The structure of claim 16, wherein said semiconductor material comprises silicon, and said source and drain regions each comprise silicide cladding at a respective surface thereof. .Iaddend..Iadd.20. The structure of claim 16, wherein said first surface is radiused near the boundary between said drain region and said channel region. .Iaddend..Iadd.21. The structure of claim 16, wherein said gate structure comprises polycrystalline silicon. .Iaddend..Iadd.22. The structure of claim 16, wherein said gate structure comprises polycrystalline silicon overlaid with silicide cladding at a surface thereof. .Iaddend.