Inverting output driver circuit for reducing electron injection into the substrate

Abstract

A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V CC . The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.

We claim: 
     
       1. A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising: first and second P-channel FETs;   first, second, third, fourth and fifth N-channel FETs;   each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;   said fifth N-channel FET having greater drive than said second P-channel FET;   the gate of the second N-channel FET being coupled to a power supply voltage (V CC ) through the second P-channel FET;   the gates of the second P-channel FET, the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;   an input node which is coupled to the gates of the first P-channel FET and the first N-channel FET;   an intermediate node that is coupled to a power supply voltage (V CC ) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;   said intermediate node being coupled to the gate of the third N-channel FET; and   a final output node that is coupled to V CC  through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the second N-channel FET through the fifth N-channel FET.   
     
     
       2. The inverting output driver circuit of claim 1, wherein said fifth N-channel FET has at least double the drive of said second P-channel FET. 
     
     
       3. The inverting output driver circuit of claim 2, wherein gate-to-source voltage is maintained at less than threshold voltage for the third N-channel FET when the potential on the final output node is less than ground potential. 
     
     
       4. A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising: first and second P-channel FETs;   first, second, third, fourth and fifth N-channel FETs;   each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;   said fifth N-channel FET having greater drive than said first P-channel FET;   the gate of the first N-channel FET being coupled to a power supply voltage (V CC ) through the second P-channel FET;   the gates of the second P-channel FET, the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;   an input node which is coupled to the gates of the first P-channel FET and the second N-channel FET;   an intermediate node that is coupled to a power supply voltage (V CC ) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;   said intermediate node being coupled to the gate of the third N-channel FET; and   a final output node that is coupled to V CC  through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the first N-channel FET through the fifth N-channel FET.   
     
     
       5. The inverting output driver circuit of claim 4, wherein said fifth N-channel FET has at least double the drive of said second P-channel FET. 
     
     
       6. The inverting output driver circuit of claim 5, wherein gate-to-source voltage is maintained at less than threshold voltage for the third N-channel FET when the potential on the final output node is less than ground potential. 
     
     
       7. An output driver circuit comprising: an N-channel pull-up field effect transistor for coupling a final output node to a power supply voltage bus;   an intermediate node coupled to the gate of said pull-up transistor;   a tri-state inverter circuit which couples an input node to said intermediate node;   means for clamping the intermediate node to the final output node whenever the intermediate node is in a low logic state, and the final output node drops more than a threshold voltage below ground potential.   
     
     
       8. The output driver circuit of claim 7, wherein said tristate inverter circuit comprises: a P-channel pull-up field-effect transistor coupled between the power supply voltage bus and said intermediate node;   a pair of N-channel pull-down field-effect transistors, said pair of N-channel FETs being series coupled between said intermediate node and a ground bus;   the gate of one of said pair being coupled to said input node, the gate of the other of said pair being coupled to the power supply voltage bus when the final output node is above ground potential, but when the output node drops below ground potential, the gate of the other of said pair is coupled to said output node;   said input node being coupled to the gate of the P-channel pull-up transistor and to the gate of one of said pair of N-channel pull-down transistors.   
     
     
       9. The output driver circuit of claim 8, wherein said means for clamping comprises means for simultaneously disconnecting the intermediate node from ground potential and means for connecting the intermediate node to the final output node, said means for disconnecting and said means for connecting being simultaneously activatable. 
     
     
       10. The output driver circuit of claim 9, wherein said means for disconnecting comprises an additional N-channel field-effect transistor in an electrical path which selectively couples said intermediate node to ground, and said means for connecting comprises still another N-channel field-effect transistor which selectively couples said intermediate node to the final output node, both instances of selective coupling occurring in response to a negative voltage at the final output node. 
     
     
       11. The output driver circuit of claim 10, wherein the gate of the N-channel field effect transistor which selectively couples said intermediate node to the final output node is permanently tied to ground potential. 
     
     
       12. The output driver circuit of claim 10, wherein the gate of the N-channel field-effect transistor in the electrical path which selectively couples said intermediate node to ground, is tied to a node which is coupled to V CC  through a device which functions as a resistor, and to the final output node through yet another N-channel field-effect transistor, the gate of this last transistor being permanently tied to ground potential. 
     
     
       13. The output driver circuit of claim 12, wherein the device which functions as a resistor is a P-channel field-effect transistor having its gate tied to ground potential. 
     
     
       14. The output driver circuit of claim 12, wherein the device which functions as a resistor is an N-channel field-effect transistor having its gate tied to V CC . 
     
     
       15. A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising: a first P-channel FET;   first, second, third, fourth and fifth N-channel FETs;   each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;   a resistive device;   said fifth N-channel FET having greater drive than said resistive device;   the gate of the second N-channel FET being coupled to a power supply voltage (V CC ) through the resistive device;   the gates of the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;   an input node which is coupled to the gates of the first P-channel FET and the first N-channel FET;   an intermediate node that is coupled to a power supply voltage (V CC ) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;   said intermediate node being coupled to the gate of the third N-channel FET; and   a final output node that is coupled to V CC  through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the second N-channel FET through the fifth N-channel FET.   
     
     
       16. The inverting output driver circuit of claim 15, wherein said resistive device is a second P-channel FET having its gate permanently held at ground potential. 
     
     
       17. The inverting output driver circuit of claim 15, wherein said resistive device is a sixth N-channel FET having its gate permanently held at a potential of V CC . 
     
     
       18. A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising: a first P-channel FET;   first, second, third, fourth and fifth N-channel FETs;   each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;   a resistive device;   said fifth N-channel FET having greater drive than said resistive device;   the gate of the first N-channel FET being coupled to a power supply voltage (V CC ) through the resistive device;   the gates of the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;   an input node which is coupled to the gates of the first P-channel FET and the second N-channel FET;   an intermediate node that is coupled to a power supply voltage (V CC ) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel-FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;   said intermediate node being coupled to the gate of the third N-channel FET; and   a final output node that is coupled to V CC  through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the first N-channel FET through the fifth N-channel FET.   
     
     
       19. The inverting output driver circuit of claim 18, wherein said resistive device is a second P-channel FET having its gate permanently held at ground potential. 
     
     
       20. The inverting output driver circuit of claim 18, wherein said resistive device is a sixth N-channel FET having its gate permanently held at a potential of V CC . .Iadd. 
     
     
       21.  An output driver circuit comprising: a P-channel FET;   a resistive device;   first, second, third, fourth, and fifth N-channel FETs; a gate of the second N-channel FET being coupled to a supply voltage through the resistive device; and   gates of the fourth and fifth N-channel FETs being coupled to a reference voltage;     an input node coupled to gates of the P-channel FET and the first N-channel FET;   an intermediate node coupled to the supply voltage through the P-channel FET and to the reference voltage through the first and second N-channel FETs; said intermediate node being coupled to a gate of the third N-channel FET; and     an output node coupled to the supply voltage through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the second N-channel FET through the fifth N-channel FET. .Iaddend..Iadd.   
     
     
       22.  The output driver circuit of claim 21 wherein the resistive device is selected from a group comprising another P-channel FET having a gate coupled to the reference voltage, a sixth N-channel FET having a gate coupled to the supply voltage, a resistor, and a strip of polycrystalline silicon. .Iaddend..Iadd.23. The output driver circuit of claim 21 wherein a drain of the first N-channel FET is coupled to the intermediate node and the source of the second N-channel FET is coupled to the reference 
     
     
        voltage. .Iaddend..Iadd.24.  An output driver circuit comprising: an output node;   a pull-up FET for coupling the output node to a supply voltage;   an intermediate node coupled to a gate of the FET;   an input node;   input circuitry for coupling the input node to the intermediate node; and   clamping circuitry for clamping the intermediate node to the output node when a voltage at the output node drops at least a threshold voltage below   
     
     
        a reference voltage. .Iaddend..Iadd.25.  The output driver circuit of claim 24 wherein the input circuitry comprises a tri-state inverter circuit. .Iaddend..Iadd.26. The output driver circuit of claim 24 wherein the pull-up FET comprises a pull-up N-channel FET. .Iaddend..Iadd.27. The output driver circuit of claim 24 wherein the input circuitry includes first and second N-channel FETs coupled in series between the intermediate node and the reference voltage, wherein the clamping circuitry comprises: a P-channel FET having a gate coupled to the reference voltage, a source coupled to the supply voltage, and a drain coupled to a gate of one of the first and second N-channel FETs;   a third N-channel FET having a gate coupled to the reference voltage, a source coupled to the output node, and a drain coupled to the drain of the P-channel FET; and   a fourth N-channel FET having a gate coupled to the reference voltage, a source coupled to the output node, and a drain coupled to the intermediate node. .Iaddend..Iadd.28. A circuit for clamping a gate of an output driver FET to a source of the output driver FET in response to an output voltage at the source dropping below a reference voltage at the gate by at least a threshold voltage, the circuit comprising:   first switching circuitry for isolating the gate from the reference voltage in response to the output voltage dropping below the reference voltage by at least the threshold voltage; and   second switching circuitry for coupling the gate to the source in response to the output voltage dropping below the reference voltage by at least the   
     
     
        threshold voltage. .Iaddend..Iadd.29.  The circuit of claim 28 wherein the first switching circuitry comprises: a first N-channel FET having a gate, a source coupled to the reference voltage, and a drain selectively coupled to the gate of the output driver FET;   a resistive device for coupling the gate of the first N-channel FET to a supply voltage; and   a second N-channel FET having a gate coupled to the reference voltage, a source coupled to the source of the output driver FET, and a drain coupled to the gate of the first N-channel FET. .Iaddend..Iadd.30. The circuit of claim 28 wherein the second switching circuitry comprises an N-channel FET having a gate coupled to the reference voltage, a source coupled to the source of the output driver FET, and a drain coupled to the gate of the output driver FET. .Iaddend.