EEPROM cell array with tight erase distribution

Abstract

An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11). The program and erase regions of each cell are physically separate from each other, and the characteristics of each of those regions may be made optimum independently from each other. Field oxide insulators (25) defining the channels (Ch) and the source line (17) have straight-line edges adjacent the source line (17) and adjacent the channel (Ch).

I claim: 
     
       1. A pair of nonvolatile arrayed memory cells in a face of a semiconductor substrate of a first conductivity-type, each cell comprising: a source in said substrate, said source having a second conductivity-type opposite said first conductivity-type;   two cell-isolation thick-field insulators, each said insulator having at least a first straight edge.[.,.]. .Iadd.and .Iaddend.a second .[.straight.]. .Iadd.etched .Iaddend.edge .[∥]. .Iadd.perpendicular .Iaddend.to said first straight edge.[., and a third straight edge perpendicular to said second and third straight edges.].;   a channel adjacent said source, said channel between said first edges of said two insulators;   a stacked floating gate and control gate over said channel and over said first edges of said insulators, said stacked floating gate and control gate having an edge parallel to said .[.third straight.]. .Iadd.second etched .Iaddend.edges of said insulators and laterally displaced from the nearest said .[.third straight.]. .Iadd.second etched .Iaddend.edges of said insulators; and   a source line formed in said substrate adjacent to said source, said source line having said second conductivity-type, said source line abutting .Iadd.said .Iaddend.second etched edges of .[.four of said insulators, said second etched edges perpendicular to said first edges.]. .Iadd.each of said insulators of each cell.Iaddend..   
     
     
       2. The memory cell pair of claim 1, each said cell including a drain formed in said substrate, said drain having said second conductivity-type, said drain opposite said channel from said source. 
     
     
       3. The memory cell pair of claim 1, each said cell including a drain formed in said substrate, said drain having said second conductivity-type, said drain opposite said channel from said source, wherein each said cell is programmable by transferring a charge to said floating gate by hot-carrier injection in response to programming voltages applied to said control gate and said drain relative to said source. 
     
     
       4. The memory cell pair of claim 1, wherein said cell is erasable by removing a charge from said floating gate by Fowler-Nordheim tunneling in response to an erasing voltage applied to said control gate relative to said source. 
     
     
       5. The memory cell pair of claim 1, wherein said width of said floating gate and said control gate masks a self-aligned implant of said source and said drain. 
     
     
       6. The memory cell pair of claim 1, each said cell including a gate-insulator layer between said floating-gate and said channel. 
     
     
       7. The memory cell pair of claim 1, wherein each said source of each said cell includes two dopants of said second conductivity-type. 
     
     
       8. The memory cell pair of claim 1, each said cell including a drain in said substrate, said drain having said second conductivity-type, said drain opposite said channel from said source, each said cell including a drain-column line connected to said drain of each said cell of said pair. 
     
     
       9. The memory cell pair of claim 1, each said cell including a drain in said substrate, said drain having said second conductivity-type, said drain opposite said channel from said source, each said cell including a drain-column line connected to said drain of each said cell of said pair, each said insulator having a fourth straight edge, wherein said connection is made between fourth straight edges of two of said insulators. 
     
     
       10. A pair of nonvolatile arrayed memory cells in a face of a semiconductor substrate of a first conductivity-type, each cell comprising: a source in said substrate, said source having a second conductivity-type opposite said first conductivity-type;   a drain in said substrate, said drain having a second conductivity-type opposite said first conductivity-type;   two cell-isolation thick-field insulators, each said insulator having at least a first straight edge.[.,.]. .Iadd.and .Iaddend.a second .[.straight.]. .Iadd.etched .Iaddend.edge .[∥]. .Iadd.perpendicular .Iaddend.to said first straight edge.[., and a third straight edge perpendicular to said second and third straight edges.].;   a channel adjacent said source, said channel between said first edges of said two insulators, said drain opposite said channel from said source;   a stacked floating gate and control gate over said channel and over said first edges of said insulators, said stacked floating gate and control gate having an edge parallel to said .[.third straight.]. .Iadd.second etched .Iaddend.edges of said insulators and laterally displaced from the nearest said .[.third straight.]. .Iadd.second etched .Iaddend.edges of said insulators; and   a gate-insulator layer between said floating-gate and said channel; and   a source line formed in said substrate adjacent to said source, said source line having said second conductivity-type, said source line abutting .Iadd.said .Iaddend.second etched edges of .[.four of said insulators, said second etched edges perpendicular to said first edges.]. .Iadd.each of said insulators of each cell.Iaddend.;   wherein each said cell is programmable by transferring a charge to said floating gate by hot-carrier injection in response to programming voltages applied to said control gate and said drain relative to said source;   wherein said cell is erasable by removing a charge from said floating gate by Fowler-Nordheim tunneling in response to an erasing voltage applied to said control gate relative to said source;   wherein .[.said.]. .Iadd.the .Iaddend.width of said floating gate and said control gate masks a self-aligned implant of said source and said drain;   wherein each said source of each said cell includes two dopants of said second conductivity-type; .Iadd.and .Iaddend.   wherein each said cell includes a drain-column line connected to said drain of each said cell of said pair.[.; and   wherein said connection is made between fourth straight edges of two of said insulators.].. .Iadd.   
     
     
       11.  A nonvolatile memory device at a face of a semiconductor substrate of a first conductivity-type, comprising: a first memory cell, said first memory cell including: a first source in said substrate, said first source having a second conductivity-type opposite said first conductivity-type;   a first pair of cell-isolation thick field insulators, each insulator of said first pair having a first insulator edge and a second insulator edge, said first insulator edge being substantially perpendicular to said second insulator edge, said second insulator edge being an etched edge;   a first channel adjacent said first source, said first channel between said first insulator edges; and   a first stacked floating gate and control gate over said first channel and over said first insulator edges, said first stacked floating gate and control gate having a first gate edge nearest to and substantially parallel to said second insulator edges and laterally displaced from said second insulator edges;     a second memory cell, said second memory cell including: a second source in said substrate, said second source having a second conductivity-type opposite said first conductivity-type;   a second pair of cell-isolation thick field insulators, each insulator of said second pair having a third insulator edge and a fourth insulator edge, said third insulator edge being substantially perpendicular to said fourth insulator edge, said fourth insulator edge being an etched edge;   a second channel adjacent said second source, said second channel between said third insulator edges; and   a second stacked floating gate and control gate over said second channel and over said third insulator edges, said second stacked floating gate and control gate having a second gate edge nearest to and substantially parallel to said fourth insulator edges and laterally displaced from said fourth insulator edges; and     source line electrically coupling said first and second sources, said first source line abutting said second and fourth insulator edges. .Iaddend..Iadd.   
     
     
       12.  The memory device of claim 11, and further comprising: a first drain formed in said substrate, said first drain having said second conductivity-type, said first drain opposite said first channel from said first source; and   a second drain formed in said substrate, said second drain having said second conductivity-type, said second drain opposite said second channel from said second source. .Iaddend..Iadd.   
     
     
       13.  The memory device of claim 12, wherein each of said cells is programmable by transferring a charge to the respective floating gate by hot-carrier injection in response to programming voltages applied to the respective control gate and the respective drain relative to the respective source. .Iaddend..Iadd.14. The memory device of claim 11, wherein each of said cells is erasable by removing a charge from the respective floating gate by Fowler-Nordheim tunneling in response to an erasing voltage applied to the respective control gate relative to the respective said source. .Iaddend..Iadd.15. The memory device of claim 11, wherein the width of each floating gate and each control gate masks a self-aligned implant of each source and each drain. .Iaddend..Iadd.16. The memory device of claim 11, wherein each of said cells includes a gate-insulator layer between the respective floating-gate channel. .Iaddend..Iadd.17. The memory device of claim 11, wherein each source of each cell includes two dopants of said second conductivity-type. 
     
     
        .Iaddend..Iadd.18.  The memory device of claim 11, and further comprising: a first drain formed in said substrate, said first drain having said second conductivity-type, said first drain opposite said first channel from said first source;   a second drain formed in said substrate, said second drain having said second conductivity-type, said second drain opposite said second channel from said second source; and   a drain-column line connected to said first drain and second drain. .Iaddend..Iadd.19. The memory device of claim 11, wherein each of said cell-isolation thick field insulators includes an indentation opposite the respective channel from the respective source, and further comprising;   a first drain formed in said substrate, said first drain having said second conductivity-type, said first drain opposite said first channel from said first source;   a second drain formed in said substrate, said second drain having said second conductivity-type, said second drain opposite said second channel from said second source; and   a drain-column line electrically coupled to said first drain proximate said indentations of said first pair of cell-isolation thick field insulators and electrically coupled to said second drain proximate said indentations of said second pair of cell-isolation thick field insulators. .Iaddend..Iadd.20. The memory cell pair of claim 1, wherein:   each of said cell-isolation thick field insulators includes an indentation opposite the respective channel from the respective source;   each memory cell further comprises a drain formed in said substrate, said drain having said second conductivity-type, said drain opposite said channel from said source; and   the memory cell pair further comprises a drain-column line electrically coupled to said drain of each memory cell proximate said indentations of said cell-isolation thick field insulators. .Iaddend.