TTL/CMOS compatible input buffer with Schmitt trigger

Abstract

A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

What is claimed is: 
     
       1. A TTL/CMOS compatible input buffer network comprising: a reference voltage generator for providing a reference voltage at a coupling electrical lead;   a Schmitt trigger input buffer coupled to said electrical lead;   said reference voltage generator comprising a reference input buffer stage having a first P-channel enhancement transistor, and first, second and third N-channel enhancement transistors;   an operational amplifier having a noninverting input terminal, an inverting input terminal, and an output lead;   a large P-channel enhancement transistor having gate, source and drain electrodes, the gate electrode of said large P-channel transistor being coupled to the output lead of said operational amplifier, and the drain electrode of said large P-channel transistor being coupled to said coupling electrical lead and to said P-channel transistor of said reference input buffer stage;   said operational amplifier, large P-channel transistor, and first P-channel transistor forming a negative feedback loop;   means for applying a fixed reference voltage to said inverting terminal of said operational amplifier;   means for connecting said noninverting terminal of said operational amplifier to the gate electrodes of said transistors of said reference input buffer stage;   said Schmitt trigger input buffer comprising a Schmitt trigger having a first P-channel enhancement transistor and first, second and third N-channel enhancement transistors; and an output stage having a native P-channel enhancement transistor and a fourth N-channel enhancement transistor, the gates of said native P-channel transistor and fourth N-channel transistor being connected to a node between said first P-channel enhancement transistor and said first N-channel enhancement transistor of said Schmitt trigger.   
     
     
       2. A TTL/CMOS compatible input buffer network as in claim 1, wherein the configuration, ratios and electrical characteristics of said P-channel and N-channel transistors of said Schmitt trigger are matched and substantially equivalent to the configuration, ratios and electrical characteristics of said P-channel and N-channel transistors respectively of said reference input buffer stage; and wherein said reference input buffer stage includes an electrical shorting connection for connecting a node between said first P-channel and said first N-channel enhancement transistors to the gate electrodes of said first P-channel and said first, second and third N-channel enhancement transistors.   
     
     
       3. A TTL/CMOS compatible input buffer network as in claim 1 .[.including.]. .Iadd.in which said means for applying a fixed reference voltage to said inverting terminal of said operational amplifier comprises; .Iaddend. first and second resistors connected in series and to a voltage source; and means for connecting said inverting input terminal of said operational amplifier to a node between said resistors.   
     
     
       4. A TTL/CMOS compatible input buffer network as in claim 1 including a large capacitor connected to said coupling electrical lead for damping noise on said reference voltage. .Iadd. 
     
     
       5.  A TTL/CMOS compatible input buffer network comprising: a Schmitt trigger circuit having a higher trigger point to rising input signals and a lower trigger point to falling input signals, and having an input line for receiving an input signal, an output line for providing an output signal, a ground terminal for being connected to a ground voltage, and a reference voltage lead which receives a reference voltage, said Schmitt trigger circuit comprising a plurality of transistors connected to form a Schmitt trigger;   a reference stage having transistors corresponding to each of said transistors of said Schmitt trigger circuit and having input and output lines, a ground terminal, and a reference voltage lead corresponding to those of said Schmitt trigger circuit, said transistors of said reference stage having length to width ratios substantially the same as corresponding transistors of said Schmitt trigger circuit, said transistors of said reference stage being connected to each other as in said Schmitt trigger circuit, and additionally said input and output lines of said reference stage being shorted together to supply a reference stage output voltage which is between said trigger points of said Schmitt trigger circuit; and   a reference voltage establishing circuit which receives a selected voltage and said reference stage output voltage, and generates said reference voltage such that said reference voltage such that said reference stage output voltage is equal to said selected voltage. .Iaddend. .Iadd.   
     
     
       6.  A TTL/CMOS compatible input buffer network as in claim 5 in which said reference voltage establishing circuit comprises: a large transistor, large enough to supply transient current for all input buffers in a system, said large transistor having a first current carrying terminal connected to a supply voltage and a second current carrying terminal for supplying said reference voltage, and a control terminal; and   an operational amplifier which: in a TTL mode receives said selected voltage and said reference stage output voltage and provides an output signal to said control terminal of said large transistor, which generates said reference voltage, and   in a CMOS mode is disabled, whereby said large transistor is fully on and provides said supply voltage as said reference voltage;     said TTL/CMOS compatible input buffer network further comprising means for switching between said TTL mode and said CMOS mode. .Iaddend. .Iadd.   
     
     
       7.  A TTL/CMOS compatible input buffer network as in claim 5 in which said reference voltage establishing circuit comprises: a large transistor having one current carrying terminal connected to a supply voltage and a second current carrying terminal for providing said reference voltage; and   an operational amplifier which receives said selected voltage on one input terminal, said reference stage output voltage on another input terminal and which provides on an output terminal a control signal for controlling said large transistor. .Iaddend.