Self-testing dynamic RAM

Abstract

Very large dynamic RAM integrated circuits are rendered self-testing by using on-chip generation of data test patterns with very high fault coverage, and concurrent testing of storage cell subarrays to reduce overall testing time. A test generator, which may operate in combination with the refresh control and timing system of the RAM integrated circuit, supplies the initial data test pattern which is loaded into the storage arrays. The conventional sense amplifier array is modified, and coupled with a gate control system for shifting data in each column of each storage subarray to an adjacent column. Alternatively, a two-terminal bilateral storage cell may be used to effect the shifting function, which effectively converts the memory into a shift register. The use of complementary data test patterns will permit detection of symmetrical faults within storage arrays.

What is claimed is: 
     
       1. A method of testing a random access memory (RAM) integrated circuit of the type having at least first and second storage arrays of storage cells, each storage array being arranged as an array of rows and columns of the storage cells, the method comprising the steps of: generating a data test pattern with a test generator and a refresh circuit, each being formed integrally with the RAM integrated circuit;   writing a selectable complement of said data test pattern into each of the first and second storage arrays;   shifting the data in each column of each storage array to an adjacent column using a plurality of shift gates whereby each row of each storage array functions as a shift register;   precharging a detection conductor to a predetermined voltage;   comparing the data stored in a column of the first storage array with the data stored in a corresponding column of the second storage array, said comparison being performed by comparator circuitry formed integrally with the RAM integrated circuit; and   subjecting said detection conductor to discharge depending upon whether said first and second storage arrays store correspondingly similar data.   
     
     
       2. The method of claim 1 wherein after said step of writing there is provided the further step of refreshing each storage cell using said refresh circuit. 
     
     
       3. The method of claim 1 wherein prior to performing said step of writing there is provided the further step of selecting an initial storage cell to be tested using a refresh circuit counter for forming addresses in the rows and columns. 
     
     
       4. The method of claim 1 wherein said step of shifting comprises the further steps of: incrementing a shift counter, and   repeating said steps of shifting and incrementing until said shift counter overflows.   
     
     
       5. The method of claim 1 wherein said step of subjecting comprises the step of applying data stored in said first and second storage arrays to respective inputs of an exclusive-OR gate. 
     
     
       6. The method of claim 1 wherein there is provided the further step of providing an indicator signal responsive to said step of subjecting. 
     
     
       7. An integrated circuit comprising: at least first and second random access memory (RAM) arrays, each formed of a plurality of storage cells for storing information organized in rows and columns, said RAM arrays being formed integrally on the integrated circuit;   first and second address decoders for selecting a desired row and column, respectively, whereby desired ones of said storage cells are identified, said address decoders .[.beings.]. .Iadd.being .Iaddend.formed integrally on the integrated circuit;   refresh circuit means coupled to said first and second address decoders for restoring an informational state of said plurality of said storage cells, said refresh circuit means being formed integrally on the integrated circuit;   counter means incorporated in said refresh circuit means for identifying a location of a defective storage cell, said counter means being formed integrally on the integrated circuit;   sense amplifier means for detecting said informational state of said storage cells, said sense amplifier means being formed integrally on the integrated circuit;   shift control means coupled to said sense amplifier means for transferring said .[.information.]. .Iadd.informational .Iaddend.state from a first one of said storage cells to a preselected second one of said storage cells;   data buffer means for conducting data signals corresponding to said informational state of said storage cells, said data buffer means being formed integrally on the integrated circuit;   test generator means coupled to said refresh circuit means and to said sense amplifier means for generating a predetermined test pattern sequence which is applied to said first and second RAM arrays, said test generator means being formed integrally on the integrated circuit; and   comparator means for comparing corresponding sequences of response signals from said first and second RAM arrays, said response signals being responsive to said predetermined test pattern sequence, said comparator means being formed integrally on the integrated circuit.   
     
     
       8. The integrated circuit of claim 7 wherein said .[.shaft.]. .Iadd.shift .Iaddend.control means comprises: return amplifier means having an input terminal coupled to an output terminal of said sense amplifier means; and   gate means responsive to a shift control signal for establishing a propagation path for propagating a signal corresponding to said informational state transferred between said first and second storage cells.   
     
     
       9. The integrated circuit of claim 8 wherein said shift control means further comprises a plurality of further sense amplifiers, each associated with a respective one of said columns, whereby each of said rows of said first and second RAM arrays is operable as a shift register. 
     
     
       10. The integrated circuit of claim 8 wherein said test generator means comprises: test step selector means for selecting said predetermined test pattern sequence;   initialization sequence generator means responsive to said test step selector means for producing a write sequence for transferring a data pattern into said RAM arrys; and   test sequence generator means coupled to said refresh circuit means and said shift control means for generating said shift control signal.   
     
     
       11. The integrated .[.circuitry.]..Iadd.circuit .Iaddend.of claim 7 comprising a further refresh circuit means for operating redundantly with said refresh circuit means. 
     
     
       12. The integrated circuit of claim 7 comprising a further data buffer means for operating redundantly with said data buffer means. 
     
     
       13. The integrated circuit of claim 7 wherein said comparator means comprises: precharge gate for establishing a predetermined logic state on a test conductor; and   comparison gate means for selectably maintaining a predetermined logic state only when said corresponding response signals from respective ones of said RAM arrays agree with one another.   
     
     
       14. The integrated circuit of claim 13 wherein said comparison gate means comprises exclusive-OR gate means having first and second inputs for receiving said corresponding response signals from said RAM arrays. 
     
     
       15. The integrated circuit of claim 7 wherein there is further provided bilateral storage cell means for receiving a logic state signal from one of said storage cells, storing said logic state signal, and transferring said logic state signal to a further one of said storage cells. 
     
     
       16. The integrated circuit of claim 15 wherein said bilateral storage cell means further comprises: storage capacitor means for storing said logic state signal; and   first and second gate means for accepting and sending said logic state signal, respectively. .Iadd.   
     
     
       17.  An apparatus for performing on-chip testing of a random access memory (RAM) integrated circuit chip, including at least two memory arrays formed of a plurality of memory cells and a refresh circuit, said apparatus comprising: test generator means, formed on said RAM integrated circuit chip and coupled to said refresh circuit, for generating a predetermined test pattern sequence of logic states on said RAM chip and for applying said predetermined test pattern to said at least two memory arrays, said test generator means including means for generating a control signal;   shift means, formed on said RAM integrated circuit chip and responsive to said control signal generated by said test generator means for shifting the logic states of said plurality of memory cells to different ones of said plurality of memory cells;   comparison means, formed on said RAM integrated circuit chip, for comparing the logic states of predetermined memory cells in said at least two memory arrays on said RAM integrated circuit chip, to detect failures in said RAM integrated circuit chip. .Iaddend. .Iadd.18. An apparatus according to claim 17, wherein said test generator means further comprises:   test step selector means for selecting said predetermined test pattern sequence; and   initialization sequence generator means responsive to said test step selector means for producing a write sequence for transferring a data pattern into said at least two memory arrays. .Iaddend. .Iadd.19. An apparatus according to claim 17, wherein said shift means includes storage means for temporarily storing said logic states of said memory cells before shifting said logic states to said different ones of said memory cells. .Iaddend. .Iadd.20. An apparatus according to claim 17, wherein said comparator means comprises:   precharge gate means for establishing a predetermined logic state on a test output line; and   comparison gate means for maintaining said predetermined logic state when the logic states of said predetermined memory cells in said at least two memory arrays are the same and for changing said predetermined logic state when the logic states of said predetermined memory cells in said at least two memory arrays are different. .Iaddend. .Iadd.21. An apparatus according to claim 17, wherein said refresh circuit includes counter means for identifying a location of a failure in said RAM integrated circuit chip. .Iaddend. .Iadd.22. An apparatus according to claim 17, wherein said plurality of memory cells are arranged in rows and columns in each of said at least two memory arrays;   wherein said apparatus further comprises:   first and second address decoders for selecting a desired row and column, respectively, in each of said at least two memory arrays. .Iaddend. .Iadd.23. An apparatus according to claim 17, wherein said shift means comprises:   a plurality of sense amplifiers; and   control means, coupled to said sense amplifiers and responsive to said control signal, for shifting the logic states of said plurality of memory cells through predetermined sense amplifiers to said different ones of said plurality of memory cells. .Iaddend. .Iadd.24. An apparatus according to claim 23, wherein said control means comprises a plurality of transistors operatively connected to receive said control signal. .Iaddend. .Iadd.25. An apparatus for performing on-chip testing of a random access memory (RAM) integrated circuit chip, including at least two memory arrays formed of a plurality of memory cells, said apparatus comprising:   first means, formed on said RAM integrated circuit chip, for generating a predetermined test pattern sequence of logic states on said RAM integrated circuit chip;   second means, formed on said RAM integrated circuit chip, for refreshing said memory cells of said at least two memory arrays;   third means, formed on said RAM integrated circuit chip, for selecting at least one test cell out of said plurality of memory cells;   fourth means, formed on said RAM integrated circuit chip, for comparing the logic states of predetermined memory cells in said at least two memory arrays;   fifth means, formed on said RAM integrated circuit chip, for generating a control signal; and   sixth means, formed on said RAM integrated circuit chip and responsive to said control signal generated by said fifth means, for shifting said logic states of said plurality of memory cells to different ones of said   
     
     
        plurality of memory cells. .Iaddend. .Iadd.26.  A method of performing on-chip testing of a random access memory (RAM) integrated circuit chip, including at least two memory arrays formed of a plurality of memory cells and a refresh circuit, the method comprising the steps of: generating a predetermined test pattern sequence of logic states on said RAM integrated circuit chip;   applying said predetermined test pattern sequence to said memory cells of said at least two memory arrays;   generating a control signal on said RAM integrated circuit chip;   shifting the logic states of said plurality of memory cells to different ones of said plurality of memory cells in response to said control signal; and   comparing the logic states of predetermined memory cells in said at least two memory arrays on said RAM integrated circuit chip to detect failures in said RAM integrated circuit chip. .Iaddend. .Iadd.27. A method according to claim 26, further comprising the step of selecting an initial storage cell to be tested using information stored in a counter in said refresh circuit. .Iaddend. .Iadd.28. A method of performing on-chip testing of a random access memory (RAM) integrated circuit chip, including at least two memory arrays formed of a plurality of memory cells, said method comprising the steps of:   generating, on said RAM integrated circuit chip, a predetermined test pattern sequence of logic states;   writing said predetermined test pattern sequence of logic states into said memory cells of said at least two memory arrays;   selecting an initial storage cell to be tested;   comparing, on said RAM integrated circuit chip, the logic states of predetermined memory cells in said at least two memory arrays;   generating a control signal on said RAM integrated circuit chip; and   shifting the logic states of said plurality of memory cells of said at least two memory arrays to different one of said plurality of memory cells in said at least two memory arrays in response to said control signal.   
     
     
        .Iaddend. .Iadd.29.  An integrated circuit comprising: at least first and second random access memory (RAM) arrays, each formed of a plurality of storage cells for storing information organized in rows and columns, said RAM arrays being formed integrally on the integrated circuit;   first and second address decoders for selecting a desired row and column, respectively, whereby desired ones of said storage cells are identified, said address decoders being formed integrally on the integrated circuit;   refresh circuit means coupled to said first and second address decoders for restoring an informational state of said plurality of said storage cells, said refresh circuit means being formed integrally on the integrated circuit;   sense amplifier means for detecting said informational state of said storage cells, said sense amplifier means being formed integrally on the integrated circuit;   data buffer means for conducting data signals corresponding to said informational state of said storage cells, said data buffer means being formed integrally on the integrated circuit;   test generator means coupled to said refresh circuit means and to said sense amplifier means for generating a predetermined test pattern sequence which is applied to said first and second RAM arrays, said predetermined test pattern sequence being generated on said integrated circuit;   comparator means for comparing corresponding sequences of response signals from said first and second RAM arrays on said integrated circuit.   
     
     
        .Iaddend. .Iadd.30.  The integrated circuit of claim 29 further comprising: return amplifier means having an input terminal coupled to an output terminal of said sense amplifier means; and   gate means responsive to a shift control signal for establishing a propagation path for propagating a signal corresponding to said informational state transferred between said first and secons storage cells. .Iaddend. .Iadd.31. The integrated circuit of claim 30 wherein there is provided a plurality of further sense amplifier means, each associated with a respective one of said columns, whereby each of said rows of said first and second RAM arrays is operable as a shift register.   
     
     
        .Iadd.32.  The integrated circuit of claim 30 wherein said test generator means comprises: test step selector means for selecting said predetermined test pattern sequence;   initialization sequence generator means responsive to said test step selector means for producing a write sequence for transferring a data pattern into said RAM arrays; and   test sequence generator means coupled to said refresh circuit means and said shift control means for generating said shift control signal. .Iaddend. .Iadd.33. The integrated circuit of claim 29 comprising a further refresh circuit means for operating redundantly with said refresh circuit means. .Iaddend. .Iadd.34. The integrated circuit of claim 29 comprising a further data buffer means for operating redundantly with said data buffer means. .Iaddend. .Iadd.35. The integrated circuit of claim 29 wherein said comparator means comprises:   precharge gate means for establishign a predetermined logic state on a test conductor; and   comparison gate means for selectably maintaining a predetermined logic state only when said corresponding response signals from respective ones of said RAM arrays agree with one another. .Iaddend. .Iadd.36. The integrated circuit of claim 35 wherein said comparison gate means comprises exclusive-OR gate means having first and second inputs for receiving said corresponding response signals from said RAM arrays.   
     
     
        .Iaddend. .Iadd.37.  The integrated circuit of claim 29 wherein there is further provided bilateral storage cell means for storing said informational state of one of the storage cells and transferring said informational state to a further one of said storage cells. .Iaddend. .Iadd.38. The integrated circuit of claim 37 wherein said bilateral storage cell means further comprises: storage capacitor means for storing said informational state; and   first and second gate means for accepting and sending said informational state, respectively. .Iaddend. .Iadd.39. A method of testing a random access memory (RAM) integrated circuit of the type having at least first and second storage arrays of storage cells, each storage array being arranged as an array of rows and columns of the storage cells, the method comprising the steps of:   generating, on said RAM integrated circuit, a data test pattern with a test generator and a refresh circuit, each being formed integrally with the RAM integrated circuit;   writing a selectable complement of said data test pattern into each of the first and second storage arrays;   shifting the data in each column of each storage array to an adjacent column using a plurality fo shift gates whereby each row of each storage array functions as a shift register; and   comparing the data stored in a column of the first storage array with the data stored in a corresponding column of the second storage array, said comparison being performed by comparator circuitry formed integrally with the RAM integrated circuit. .Iaddend. .Iadd.40. The method of claim 39 wherein after said step of writing there is provided the further step of refreshing each storage cell using said refresh circuit. .Iaddend. .Iadd.41. The method of claim 39 wherein prior to performing said step of writing there is provided the further step of selecting an initial storage cell to be tested using a refresh circuit counter for forming addresses in the rows and columns. .Iaddend. .Iadd.42. The method of claim 39 wherein said step of shifting comprises the further steps of:   incrementing a shift counter; and   repeating said steps of shifting and incrementing until said shift counter overflows. .Iaddend.