Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage

Abstract

The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit. Thus, the register to register data transfers within the CPU are overlapped with the data transfers over the I/O bus to main storage. The data transfers to and from main storage are generally considerably longer than the simpler register to register data transfer. The apparatus may be operated so that several register to register transfers may take place during the time required for a transfer of data to or from the external storage unit. The present invention further includes means for dynamically determining data dependencies between the register to register transfers and the I/O bus transfers.

We claim: 
     
       1. In a data processing system including a CPU, at least one external unit requiring data from or providing data to said CPU and an I/O bus for the transfer of said data between said CPU and external unit, said CPU comprising: means for executing a sequence of instructions including a first instruction;   means connected to the executing means for transferring data to or from said external unit over said bus during synchronized CPU time cycles,   means connected to the executing means for storing data in a plurality of registers within said CPU,   means connected to the transferring means and storing means for internally transferring data within said CPU registers concurrently during the transfer of data to or from the external unit, and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data wherein the transfer of data between CPU registers coincides with the transfer of data to or from the external unit, said control means further including means for determining when data required for execution of a first of a sequence of instructions in said CPU has not been stored in one or more of the CPU registers as required by the first instruction and   delaying the execution of the first instruction until such data is stored in the one or more registers while permitting the execution of other instructions of said sequence that do not require any data resulting from the execution of said first instruction.     
     
     
       2. The data processing system of claim 1 wherein said external unit is an external data storage unit. 
     
     
       3. The data processing system of claim 2 wherein said control means includes means for generating data transfer commands to the external unit transfer means,   means for assigning a register in said CPU storing means to which data is to be transferred, and   means connected to said assigning means for storing a tag identifying said assigned register in a tag register in the control means, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer command, for clearing said tag in the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared.   
     
     
       4. The data processing system of claim 3 wherein said control means further includes means for cancelling a previous data transfer command in the event that a subsequent data transfer command assigns the same register assigned by the previous command before the previous command transfer is completed.   
     
     
       5. The data processing system of claim 4 wherein said storing means includes means for generating register to register transfer commands, and   said control means further includes means for comparing said register to register transfer commands to said stored tags and for cancelling a previous data transfer command in the event that a subsequent register to register transfer command transfers data to the same register assigned by the previous command before the previous command transfer is completed.   
     
     
       6. The data processing system of claim 5 wherein said transfers to and from said external unit require a greater number of CPU time cycles than do said register to register transfers. .Iadd. 
     
     
       7.  The data processing system of claim 6 wherein said control means further includes means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available. .Iaddend. .Iadd.8. In a data processing system including a CPU, at least one external unit requiring data from or providing data to said CPU and an I/O bus for the transfer of said data between said CPU and external unit, said CPU comprising:   means for executing a sequence of instructions;   means connected to the executing means for transferring data to or from said external unit over said bus;   means connected to the executing means for storing data in a plurality of registers within said CPU;   means connected to the transferring means and storing means for internally transferring data within said CPU registers concurrently during the transfer of data to or from the external unit; and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data wherein the transfer of data between CPU registers coincides with the transfer of data to or from the external unit, said control means further including means for determining when data to be loaded into first one or more of the CPU registers by execution of a first of a sequence of instructions in said CPU has not been loaded in first one or more of the CPU registers as required by the first instruction   determining when data to be loaded into second one or more of the CPU registers by execution of a second within the sequence of instructions in said CPU has not been loaded in second one or more of the CPU registers as required by the second instruction and   simultaneously waiting for completion of execution of the first and second instructions while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of     
     
     
        execution of said first or second instructions. .Iaddend. .Iadd.9.  The data processing system of claim 8 wherein said external unit is an external data storage unit. .Iaddend. .Iadd.10. The data processing system of claim 9 wherein said control means includes means for generating data transfer commands to the external unit transfer means,   means for assigning a register in said CPU storing means to which data is to be transferred, and   means connected to said assigning means for storing a tag identifying said assigned register in a tag register in the control means, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer command, for clearing said tag in the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared. .Iaddend. .Iadd.11. The data processing system of claim 10 wherein said control means further includes   means for cancelling a previous data transfer command in the event that a subsequent data transfer command assigns the same register assigned by the previous command before the previous command transfer is completed.   
     
     
        .Iaddend. .Iadd.12.  The data processing system of claim 11 wherein said storing means includes means for generating register to register transfer commands, and   said control means further includes means for comparing said register to register transfer commands to said stored tag and for cancelling a previous data transfer command in the event that a subsequent register to register transfer command transfers data to the same register assigned by the previous command before the previous command transfer is completed. .Iaddend. .Iadd.13. The data processing system of claim 12 wherein said transfers to and from said external unit require a greater number of CPU time cycles than do said register to register transfers. .Iaddend. .Iadd.14. The data processing system of claim 10 wherein said control means further includes   means for assigning each one of the plurality of registers in said CPU storing means to which data is to be transferred,   a plurality of tag registers,   means for storing a tag identifying each of said assigned registers in one of the plurality of tag registers, for comparing subsequent data transfer commands to each of the stored tags to determine if data for these subsequent data transfer commands includes data resulting from one of the external unit transfer commands, for clearing one of the plurality of tags in the tag register when its respective external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared, and   means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available.   
     
     
        .Iaddend. .Iadd.15.  The data processing system of claim 14 wherein said control means further includes means for clearing any one of the plurality of tags in the tag register when its respective external unit data transfer is complete, irrespective of the order in which the tags were assigned. .Iaddend. .Iadd.16. A data processing system comprising: means for executing a sequence of instructions;   means connected to the executing means for storing data in a plurality of registers;   means connected to the executing means and storing means for transferring data between registers concurrently during the transfer of data to or from an external unit, and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data and further including means for determining when data to be loaded into one or more registers by execution of at least two instructions in a sequence of instructions has not been loaded in one or more of the registers as required by the at least two instructions, and   waiting for completion of execution of the at least two instructions while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of execution of either of said at least two instructions. .Iaddend. .Iadd.17. The data processing system of claim 16 wherein said control means includes     means for generating data transfer commands to the external unit transfer means,   means for assigning a register in said CPU storing means to which data is to be transferred, and   means connected to said assigning means for storing a tag identifying said assigned register in a tag register in the control means, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer command, for clearing said tag in the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has   
     
     
        been cleared. .Iaddend. .Iadd.18.  The data processing system of claim 17 wherein said control means further includes means for cancelling a previous data transfer command in the event that a subsequent data transfer command assigns the same register assigned by the previous command before the previous command transfer is completed. .Iaddend. .Iadd.19. The data processing system of claim 18 wherein said storing means includes means for generating register to register transfer commands, and   said control means further includes means for comparing said register to register transfer commands to said stored tags and for cancelling a previous data transfer to the same register assigned by the subsequent command before the previous command transfer is completed. .Iaddend. .Iadd.20. The data processing system of claim 17 wherein said control means further includes   means for assigning each one of the plurality of registers in said CPU storing means to which data is to be transferred,   a plurality of tag registers,   means for storing a tag identifying each of said assigned registers in one of the plurality of tag registers, for comparing subsequent data transfer commands to each of the stored tags to determine if data for these subsequent data transfer commands includes data resulting from one of the external unit transfer commands, for clearing one of the plurality of tags in the tag registers when its respective external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared, and   means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available.   
     
     
        .Iaddend. .Iadd.21.  The data processing system of claim 20 wherein said control means further includes means for clearing any one of the plurality of tags in the tag register when its respective external unit data transfer is complete, irrespective of the order in which the tags were 
     
     
        assigned. .Iaddend. .Iadd.22.  A data processing system comprising: means for executing a sequence of instructions;   means connected to the executing means for storing data in a plurality of registers;   means connected to the executing means and storing means for transferring data between registers concurrently during the transfer of data to or from an external unit, and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data and further including means for determining when data to be loaded in one or more of the CPU registers by execution of an instruction in a sequence of instructions has not been loaded in said one or more of the registers as required by the instruction and   waiting for completion of execution of the instruction until either data required by said instruction is stored in said one or more registers or until a subsequent instruction in said sequence is encountered which will result in data being loaded in the same one or more registers, while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of execution of the     
     
     
        instruction. .Iaddend. .Iadd.23.  The data processing system of claim 22 wherein said control means includes means for generating data transfer commands to the external unit transfer means,   means for assigning a register in said CPU storing means to which data is to be transferred, and   means connected to said assigning means for storing a tag identifying said assigned register in a tag register in the control means, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer command, for clearing said tag in the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has   
     
     
        been cleared. .Iaddend. .Iadd.24.  The data processing system of claim 23 wherein said control means further includes: means for cancelling a previous data transfer command in the event that a subsequent data transfer command assigns the same register assigned by the previous command before the previous command transfer is completed.   
     
     
        .Iaddend. .Iadd.25.  The data processing system of claim 24 wherein said storing means includes means for generating register to register transfer commands, and said control means further includes means for comparing said register to register transfer commands to said stored tags and for cancelling a previous data transfer command in the event that a subsequent register to register transfer command transfers data to the same register assigned by the previous command before the previous command transfer is completed. .Iaddend. .Iadd.26. The data processing of claim 23 wherein said control means further includes   means for assigning each one of the plurality of registers in said CPU storing means to which data is to be transferred,   a plurality of tag registers,   means for storing a tag identifying each of said assigned registers in one of the plurality of tag registers, for comparing subsequent data transfer commands to each of the stored tags to determine if data for these subsequent data transfer commands includes data resulting from one of the external unit transfer commands, for clearing one of the plurality of tags in the tag registers when its respective external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared, and   means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available.   
     
     
        .Iaddend. .Iadd.27.  The data processing system of claim 26 wherein said control means further includes means for clearing any one of the plurality of tags in the tag register when its respective external unit data transfer is complete, irrespective of the order in which the tags were assigned. .Iaddend. .Iadd.28. A data processing system comprising: means for executing a sequence of instructions;   means connected to the executing means for storing data in a plurality of registers;   means connected to the executing means and storing means for transferring data within registers concurrently during the transfer of data to or from an external unit, and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data and further including means for determining when data to be loaded into one or more of the CPU registers by execution of at least two instructions in a sequence of instructions has not been stored in one or more of the registers as required by the at least two instructions and   waiting for the completion of execution of the at least two instructions until either data required by said instructions is stored in said one or more registers or until a subsequent instruction in said sequence is encountered which will result in data being loaded in the same one or more registers, while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of execution of said at least two instructions. .Iaddend. .Iadd.29. The data processing system of claim 28 wherein said control means includes     means for generating data transfer commands to the external unit transfer means,   means for assigning a register in said storing means to which data is to be transferred, and   means connected to said assigning means for storing a tag identifying said assigned register in a tag register in the control means, for comparing subsequent data transfer commands to the stored tags to determine if data for these subsequent data transfer commands includes data resulting from the external unit transfer command, for clearing said tag in the tag register when the external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has   
     
     
        been cleared. .Iaddend. .Iadd.30.  The data processing system of claim 29 wherein said control means further includes: means for cancelling a previous data transfer command in the event that a subsequent data transfer command assigns the same register assigned by the previous command before the previous command transfer is completed. .Iaddend. .Iadd.31. The data processing system of claim 30 wherein said storing means includes means for generating register to register transfer commands, and   said control means further includes means for comparing said register to register transfer commands to said stored tags and for cancelling a previous data transfer command in the event that a subsequent register to register transfer command transfers data to the same register assigned by the previous command before the previous command transfer is completed. .Iaddend. .Iadd.32. The data processing system of claim 29 wherein said control means further includes   means for assigning each one of the plurality of registers in said CPU storing means to which data is to be transferred,   a plurality of tag registers,   means for storing a tag identifying each of said assigned registers in one of the plurality of tag registers, for comparing subsequent data transfer commands to each of the stored tags to determine if data for these subsequent data transfer commands includes data resulting from one of the external unit transfer commands, for clearing one of the plurality of tags in the tag registers when its respective external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared, and   means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available.   
     
     
        .Iaddend. .Iadd.33.  The data processing system of claim 32 wherein said control means further includes means for clearing any one of the plurality of tags in the tag register when its respective external unit data transfer is complete, irrespective of the order in which the tags were assigned. .Iaddend. .Iadd.34. A data processing system, comprising: means for executing a sequence of instructions;   means connected to the executing means for storing data in a plurality of registers;   means connected to the executing means and the storing means for transferring data between registers concurrently during transfer of data to or from an external unit; and   control means connected to the executing means, transferring means and storing means for controlling the transfer of data, said control means including means for determining when data to be stored in at least a first register by execution of a first instruction in said sequence of instructions has not been stored in said first register,   determining when data to be stored in at least a second register by execution of a second instruction in said sequence of instructions has not been stored in said second register,   waiting for the completion of execution of said first instruction until data is loaded in said first register, while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of execution of said first instruction,   concurrently waiting for the completion of execution of said second instruction until data is loaded in said second register, while permitting the execution of other instructions of said sequence that do not require any data resulting from the completion of execution of said second instruction, and   cancelling the execution of either of said first or second instructions if any of said other instructions of said sequence designate either said first or second registers as a destination register before completion of execution of said first or second instruction, respectively. .Iaddend.     
     
     
        .Iadd.35.  The data processing system of claim 34 wherein said control means further includes means for assigning each one of the plurality of registers in said CPU storing means to which data is to be transferred,   a plurality of tag registers,   means for storing a tag identifying each of said assigned registers in one of the plurality of tag registers, for comparing subsequent data transfer commands to each of the stored tags to determine if data for these subsequent data transfer commands includes data resulting from one of the external unit transfer commands, for clearing one of the plurality of tags in the tag registers when its respective external unit data transfer is complete, and for delaying the execution of any subsequent data transfer commands requiring data from the result of this external unit data transfer until the tag has been cleared, and   means for delaying the execution of any subsequent instruction requiring the assignment of a register when there are no tag registers available. .Iaddend. .Iadd.36. The data processing system of claim 35 wherein said control means further includes means for clearing any one of the plurality of tags in the tag register when its respective external unit data transfer is complete, irrespective of the order to which the tags were assigned. .Iaddend.