Self referenced sense amplifier

Abstract

A sense amplifier with two input control stages whose input voltages are equalized during a precharge cycle by a switching means.

What is claimed is: 
     
       1. A sense amplifier for use in connection with a signal line to read information appearing as binary signals on said signal line during READ operations, said signal line being precharged before each READ operation, said sense amplifier comprising a first control stage including first and second series connected enhancement type FETs, the gate of said first FET being connectable to said signal line, said first control stage having an output connected between its FETs, the gate of said second FET being connected to said output; a second control stage including first and second series connected enhancement type FETs, the gate of said first FET of the second stage being connected to said signal line, the gate of said second FET of said second stage being connected to the output of the first control stage, said second control stage having an output connected between its FETs; an output stage including first and second series connected enhancement type FETs, the gate of said first FET of said output stage being connectable to said signal line, the gate of said second FET of said output stage being connected to the output of said second control stage, said output stage having an output means connected between its FETs; and switching means connecting the gates of the first FETs of said first control stage and said output stage to said signal line prior to each READ operation and disconnecting them therefrom at the start of each READ operation. 
     
     
       2. A sense amplifier according to claim 1, wherein said switching means includes an enhancement type FET which is turned on prior to each READ operation to equalize the voltage on the gate of the first FET of the first stage with that on the gate of the first FET of the second stage during the precharge preceding each READ operation. 
     
     
       3. A sense amplifier according to claim 2, wherein all of said FETs are in a first condition during the precharge preceding each READ operation and wherein said switching means FET is turned off at the start of each READ operation whereby if said signal line has a binary 1 applied along it during a READ operation all of said FETs remain in said first condition to signify said binary 1 and if said signal line has a binary 0 applied along it during a read operation the first FET of said second stage and the second FET of said output stage switch to a second condition during the READ operation to signify said binary 0. 
     
     
       4. A sense amplifier according to claim 3, wherein a capacitor is connected between the gate of said first FET of said output stage and the drain of said second FET thereof to increase the speed at which said output stage signifies the application of a binary 0 along said signal line over the speed at which it would so signify in the absence of said capacitor. 
     
     
       5. A sense amplifier according to claim 4, wherein said output stage includes a Schmitt trigger connected as the output means of said output stage. 
     
     
       6. A sense amplifier according to claim 5 including a discharge means discharging the gate of the first FET of said first stage at the end of each READ operation. 
     
     
       7. A sense amplifier according to claim 6, wherein the discharge means includes a single pulse generator and an enhancement type discharge FET connected between the gate of said first FET of said first stage and ground, said generator producing a single pulse at the end of each READ operation which turns on said discharge FET to connect the gate of the first FET of said first stage to ground. 
     
     
       8. A sense amplifier as in claim 7, wherein said switching means includes a second enhancement type FET through which the first enhancement type FET of said switching means is controlled to be turned on prior to each READ operation and to be turned off at the start of each READ operation. .Iadd. 
     
     
       9.  A sense amplifier for use in connection with a signal line to read information appearing as binary signals on said signal line during READ operations, said signal line having a precharge voltage on it before each READ operation, said sense amplifier comprising sensing means connectable to said signal line and switching means connected to said sensing means, said switching means switching from a first condition to a second condition at the beginning of a READ operation to cause to be applied to said sensing means during said READ operation a predetermined voltage which is prescribed by the precharge voltage appearing on said signal line prior to said READ operation, said sensing means switching from a first to a second condition or not during said READ operation depending on the state of the binary signal appearing on said signal line during said READ operation, and wherein said sensing means comprises a first control means and a second means connected to each other, said first means being connected to said signal line through said switching means before a READ operation and disconnected from it during a READ operation, said second means being connected to said signal line both before and during a READ operation. .Iaddend. .Iadd. 
     
     
       10.  A sense amplifier as in claim 9, wherein said first means has a first and second state, said first means being in said first state when connected to said signal line before a READ operation and remaining in said first condition during a READ operation. .Iaddend. .Iadd.11. A sense amplifier as in claim 10, wherein said first means includes first and second series connected FETs, the gate of the first FET being connected to said signal line prior to a READ operation, said first means having an 
     
     
        output between its FETs. .Iaddend. .Iadd.12.  A sense amplifier as in claim 11 wherein said second means includes first and second series connected FETs, the gate of said first FET of said second means being connected to said signal line, the gate of said second FET of said second means being connected to said output of said first means, said second means having an output between its FETs. .Iaddend. .Iadd.13. A sense amplifier as in claim 12, including a discharge means discharging the gate of the first FET of said first means at the end of each READ operation. .Iaddend. .Iadd.14. A sense amplifier as in claim 13, wherein the discharge means includes a single pulse generator and an enhancement type FET connected between the gate of said first FET of said first means and ground, said generator producing a single pulse at the end of each READ operation which turns on said enhancement type FET to connect the gate of the first FET of said first means to ground. .Iaddend. .Iadd.15. A sense amplifier as in claim 14, wherein said switching means includes an enhancement type FET which is turned on prior to each READ operation to equalize the voltage on the gate of the first FET of the first means with that on the gate of the first FET of the second means during the precharge 
     
     
        preceding each READ operation. .Iaddend. .Iadd.16.  A sense amplifier as in claim 15, wherein said switching means includes a second enhancement type FET through which the first enhancement type FET of said switching means is controlled to be turned on prior to each READ operation and to be turned off at the start of each READ operation. .Iaddend.