Dynamic memory array with segmented bit lines

Abstract

A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells with a different sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.

What is claimed is: 
     
       1. A semiconductor memory device comprising: an array of rows and columns of memory cells, each cell including .[.an access.]. .Iadd.a .Iaddend.transistor having a gate connected to one of a plurality of parallel word lines extending along said rows of cells, each cell including storage means coupled to a source-to-drain path of said .[.access.]. transistor,   a plurality of bit lines extending along said columns of cells perpendicular to .Iadd.and vertically spaced from .Iaddend.said word lines,   a plurality of bit line segments for each of said bit lines, said segments being .[.separate.]. .Iadd.at least partially formed at a level vertically spaced .Iaddend.from said bit lines and extending parallel to said bit lines, the source-to-drain paths of said .[.access.]. transistors being connected to said segments, and a plurality of control means, a separate one of said control means being connected between each of said segments and a corresponding one of said bit lines for selectively connecting said segments to a bit line in response to an address.   
     
     
       2. A device according to claim 1 including a plurality of differential sense amplifiers, each sense amplifier having two inputs, each input coupled to a different one of said bit lines. 
     
     
       3. A device according to claim 2 including row addressing means for receiving said address and activating said control means; said row addressing means also activating a selected one of said word lines in response to said address. 
     
     
       4. A device according to claim 2 wherein the capacitance per unit length of said bit lines is much less than that of said segments. 
     
     
       5. A device according to claim 1 wherein said storage means in each cell is a capacitor. 
     
     
       6. A device according to claim 1 wherein there are a plurality of said cells connected to each of said segments. 
     
     
       7. A device according to claim 6 wherein there is at least eight segments per bit line and at least eight cells per segment. 
     
     
       8. A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in a face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell,   a plurality of bit lines extending along said face above said word lines and over said columns of cells, the bit lines being perpendicular to said word lines,   a plurality of bit-line segments for each of said bit lines, said segments being .[.separate.]. .Iadd.at least partially formed at a level vertically spaced .Iaddend.from said bit lines and extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments,   and a plurality of separate control means, one control means for each of said segments, each of said control means selectively connecting each said segment to a bit line.   
     
     
       9. A device according to claim 8 including a plurality of differential sense amplifiers, one of said sense amplifiers for each column, each sense amplifier having two inputs, each input coupled to a different one of a pair of said bit lines. 
     
     
       10. A device according to claim 9 including row addressing means for receiving an address and selectively activating said control means in response to said address; said row addressing means also activating a selected one of said word lines in response to said address. 
     
     
       11. A device according to claim 8 wherein the capacitance per unit length of said bit lines is much less than that of said segments. 
     
     
       12. A device according to claim 8 wherein said segments are formed by heavily-doped regions in said face. 
     
     
       13. A device according to claim 8 wherein there is at least eight segments per bit line and at least eight cells per segment. 
     
     
       14. In a semiconductor memory device: a plurality of memory cells in a column, each cell including .[.an access.]. .Iadd.a .Iaddend.transistor having a gate, each cell including storage means coupled to a source-to-drain path of said transistor,   a bit line extending along said column of cells,   a plurality of bit line segments for said bit line, each of said segments being .[.separate.]. .Iadd.at least partially formed at a level vertically spaced .Iaddend.from said bit line and extending parallel to said bit line, the source-to-drain paths of a plurality of said .[.access.]. transistors being connected to each of said segments,   and a plurality of control means, each control means separately and selectively connecting one of said segments to one of said bit lines.   
     
     
       15. A device according to claim 14 including at least two of said bit lines, and a different sense amplifier having two inputs, each input coupled to one of said two bit lines. 
     
     
       16. A device according to claim 14 including addressing means for receiving an address and selectively activating said control means; said addressing means also activating a selected one of said gates in response to said address. 
     
     
       17. A device according to claim 14 wherein the capacitance per unit length of said bit line is much less than that of said segments. 
     
     
       18. A device according to claim 14 wherein there are at least eight of said segments and at least eight of said cells for each segment. 
     
     
       19. A device according to claim 14 wherein said storage means in each cell is a capacitor. 
     
     
       20. A device according to claim 19 wherein said control means are transistors having source-to-drain paths connected to said bit line. .Iadd. 
     
     
       21.  A semiconductor memory device comprising: an array of rows and columns of memory cells, each cell including a transistor having a gate connected to one of a plurality of parallel word lines extending along said rows of cells, each cell including storage means coupled to a source-to-drain path of said transistor,   a plurality of bit lines extending along said columns of cells perpendicular to and vertically spaced from said word lines,   at least one bit line segment for each of said bit lines, said segment being at least partially formed at a level vertically spaced from said bit lines and extending parallel to said bit lines, the source-to-drain paths of a plurality of said transistors being connected to said at least one segment, and a plurality of control means, a separate one of said control means connected between each of said at least one bit line segment and a corresponding one of said bit lines for selectively connecting said segment to a bit line in response to an address. .Iaddend. .Iadd.   
     
     
       22.  A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in the face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell,   a plurality of bit lines extending along said face above said word lines and over said columns of cells, the bit lines being perpendicular to said word lines,   at least one bit line segment for each of said bit lines, said segment being at least partially formed at a level vertically spaced from said bit lines and extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to said at least one bit line segment,   and a plurality of separate control means, one control means for each said at least one bit line segment, each of said control means selectively connecting each said at least one bit line segment to a bit line. .Iaddend. .Iadd.   
     
     
       23.  A device according to claim 21, wherein said column comprises memory cells coupled to at least two bit line segments. .Iaddend. .Iadd.24. A device according to claim 22, wherein said columns comprise memory cells coupled to at least two bit line segments. .Iaddend. .Iadd.25. A semiconductor memory device comprising: (a) a plurality of memory cells in a column, each cell including a transistor having a gate and a storage unit coupled to the source-to-drain path of said transistor;   (b) a bit line extending along said column of cells;   (c) at least two segments for said bit line, each segment being at least partially formed at a level vertically spaced from said bit line and extending substantially parallel to said bit line, the source-to-drain path of a plurality of transistors coupled to each of said segments; and   (d) a plurality of control devices, one control device separately and selectively coupling each of said segments to said bit line. .Iaddend. .Iadd.26. A device according to claim 25, wherein said columns comprise memory cells coupled to at least two bit line segments. .Iaddend.   
     
     
        .Iadd.     A device as in claim 25 including a substrate with the source-to-drain paths of said transistors disposed therein. .Iaddend. .Iadd.28. A device as in claim 27 wherein said storage unit capacitively couples to said substrate. .Iaddend. .Iadd.29. A device as in claim 28 wherein said storage unit is a capacitor in electrical communication with 
     
     
        the source-to-drain paths of said transistors. .Iaddend. .Iadd.30.  A device as in claim 25 wherein said storage unit is a capacitor in electrical communication with the source-to-drain paths of said transistors. .Iaddend. .Iadd.31. A device as in claim 25 wherein each segment has at least 8 cells coupled thereto. .Iaddend.