Digital signal detecting and compensating circuit with adjustable window signal

Abstract

In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated by frame synchronizing signals into frames, each having a predetermined frame period, the combination comprising a detecting circuit which detects the frame synchronizing signals and generates respective detection signals in response thereto, a gating circuit which receives the detection signals and which gates the latter in response to gating signals, and a windowing circuit which generates window signals of a predetermined length in response to the detection signals and which supplies the window signals as the gating signals to the gating circuit.

What is claimed is: 
     
       1. In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated by frame synchronizing signals, each having a predetermined frame period, the combination comprising: detecting means for detecting said frame synchronizing signals and generating respective detection signals in response thereto;   gating means receiving said detection signals for gating the latter in response to gating signals; and   windowing means including first means for supplying first window signals of a first predetermined length synchronized with said detection signals as said gating signals to said gating means, and second means for supplying second window signals of a second predetermined length as said gating signals to said gating means when a plurality of .[.said.]. .Iadd.gated .Iaddend.detection signals are not .[.generated.]. .Iadd.output by said gating means, .Iaddend.said second predetermined length being greater than said first predetermined length.   
     
     
       2. The circuit of claim 1; wherein said second means includes supervisory means for detecting deviations in phase between said first window signals and said detection signals .[.as gated by said gating means.]. and for supplying said second window signals to said first means to vary the timing of said first window signals in the sense to correct said deviations therebetween. 
     
     
       3. The circuit of claim 2; and wherein said apparatus for reproducing has a servo circuit responsive to said second window signals supplied by said supervisory means for operating said apparatus for reproducing at a predetermined speed suitable for said reproducing of said digital signal. 
     
     
       4. The circuit of claim 3, wherein said servo circuit includes speed control means for effecting small changes in said operating speed of said apparatus, and wherein said second window signals from said supervisory means selectively actuate said speed control means. 
     
     
       5. The circuit of claim 1; wherein said first means includes: clock means for generating clock signals corresponding to said frame periods of said digital .[.signals.]. .Iadd.signal .Iaddend.and counter means for counting said clock signals and for generating said first window signals when a count derived therefrom .[.exceeds a.]. .Iadd.corresponds to .Iaddend.predetermined .[.value.]. .Iadd.values. .Iaddend.   
     
     
       6. The circuit of claim 5; wherein said detection signals gated by said gating means reset said counter means to a predetermined value. 
     
     
       7. The circuit of claim 5; wherein said windowing means includes means for determining said predetermined length of said first window signals. 
     
     
       8. The circuit of claim 7; wherein said means for determining includes: means for determining a beginning time of each of said first window signals and for generating a beginning signal in response thereto; and   means for determining an end time of each of said first window signals and for generating an end signal in response thereto.   
     
     
       9. The circuit of claim 8, wherein said means for determining a beginning time is connected to said clock means and generates a count corresponding to said predetermined frame period less one-half of said predetermined length of said first window signals to determine said beginning signal, and wherein said means for determining an end time is connected to said clock means and generates a count corresponding to one-half of said predetermined length of said first window signals to determine said end signal. 
     
     
       10. The circuit of claim 8, .Iadd.wherein said second means includes supervisory means for detecting deviations in phase between said first window signals and said detection signals and .Iaddend.in which said .Iadd.supervisory means includes .Iaddend.counter means .Iadd.that .Iaddend.receives clock signals for operation therewith; and wherein said end signals are supplied to said counter means as said clock signals. 
     
     
       11. The circuit of claim 7; wherein said first means includes generating means connected to said means for determining for generating said first window signals with said first predetermined length; .Iadd.said second means includes supervisory means for detecting deviations in phase between said first window signals and said detection signals for supplying said second window signals; .Iaddend.and said windowing means includes OR gate means for receiving said .Iadd.first and second .Iaddend.window signals from .[.both.]. said generating means and said supervisory means.Iadd., respectively, .Iaddend.and for supplying said window signals to said gating means. 
     
     
       12. The circuit of claim 11; wherein said generating means is a flip-flop circuit. 
     
     
       13. The circuit of claim 7; wherein said supervisory means includes controller means for supplying control signals to said means for determining to vary said first predetermined length of said first window signals. 
     
     
       14. The circuit of claim 13, in which said apparatus for reproducing is operable in a plurality of modes; and further comprising system controller means for supplying signals to said controller means to vary said first predetermined length of said first window signals in accordance with said modes of said apparatus for reproducing. 
     
     
       15. The circuit of claim 13, in which said digital signal has a plurality of states; and further comprising RF detector means for detecting said states of said digital signal and supplying signals to said controller means to vary said predetermined length of said first window signals in response thereto. 
     
     
       16. The circuit of claim 13; and further comprising error correction means for supplying signals to said controller means to vary said first predetermined length of said first window signals in response to errors in said digital signal. .[. 
     
     
       17.  The circuit of claim 5; wherein said clock means includes: a clock generator for generating clock pulses synchronized with said frame period; and   counter means for counting said clock pulses from said clock generator..]. .Iadd.   
     
     
       18.  In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated into predetermined frame periods by frame synchronizing signals, the combination comprising: means for receiving a reproduced digital signal;   synch detector means for detecting the frame synchronizing signals from the reproduced digital signal and generating detection signals in response thereto;   gating means receiving the detection signals for gating the latter in response to window pulses fed thereto as a gating signal;   clock means for generating clock signals;   counter means for counting said clock signals up to a first predetermined number (n) corresponding to the predetermined frame period;   window signal generating means including first detecting means connected to said counter means for detecting the count of said counter means and generating gate-open signals when the count of said counter means is equal to a second predetermined number that is less than the first predetermined number (n) at a first predetermined time following occurrence of the detection signals to determine a beginning time of each window pulse of the gating signal fed to said gating means; and   said window signal generating means further including second detecting means connected to said counter means for detecting the count of said counter means and generating gate-close signals when the count of said counter means is equal to a third predetermined number less than the second predetermined number at a second predetermined time following occurrence of the detection signals to determine an end time of each window pulse of the gating signal. .Iaddend. .Iadd.19. The circuit of claim 18; wherein each window pulse of the gating signal is substantially centered relative to each of said detection signals from said signal detector means. .Iaddend. .Iadd.20. The circuit of claim 18; wherein said window signal generating means includes a flip-flop circuit connected to said first detecting means and said second detecting means for generating said window pulse. .Iaddend. .Iadd.21. The circuit of claim 18; wherein said window pulse has a predetermined initial length and said first detecting means generates said gate-open signals when the count of said counter means corresponds to said predetermined frame period of less one-half of the predetermined initial length of said window pulse and said second detecting means supplies the gate-close signals when the count of said counter means corresponds to one-half of the predetermined initial length of said window pulse. .Iaddend. .Iadd.22. The circuit of claim 21; further comprising controller means for supplying control signals to said window signal generating means for determining said first predetermined   
     
     
        time. .Iaddend. .Iadd.23.  The circuit of claim 22; wherein said apparatus reproduces said digital signal in different modes and said controller means determines said first predetermined time in accordance with said different reproducing modes of the reproduced signal. .Iaddend. .Iadd.24. The circuit of claim 23; wherein said digital signal has a plurality of states, and further comprising third detecting means for detecting the state in which said digital signal is reproduced and supplying an output signal to said controller means to determine the first predetermined time in response thereto. .Iaddend. .Iadd.25. The circuit of claim 23; further comprising error correction means for detecting errors in the reproduced digital signal and supplying signals to said controller means to determine said first predetermined time in response to detected errors in said digital signal. .Iaddend. .Iadd.26. In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated into predetermined frame periods by frame synchronizing signals, the combination comprising: detecting means receiving the reproduced digital signal for detecting said frame synchronizing signals and generating detection signals in response thereto;   gating means receiving said detection signals for gating the latter in response to gating signals;   windowing means including first means for supplying first window signals synchronized with said detection signals from said detecting means as said gating signals to said gating means and second means for supplying second window signals of length longer than said first window signals as said gating signals to said gating means in the absence of a plurality of gated detection signals from said gating means;   said second means including means for detecting deviations in phase between said first window signals and said detection signals gated by said gating means and producing a corresponding output, and counter means receiving said output from said means for detecting deviations for supplying said second window signals to said gating means when a count in said counter means exceeds a predetermined value. .Iaddend. .Iadd.27. The circuit of claim 26; in which said apparatus includes a plurality of operating modes and further comprising controller means for determining said predetermined value in said counter means in accordance with said plurality of reproducing modes. .Iaddend. .Iadd.28. The circuit of claim 26; wherein said apparatus includes a plurality of operating modes and said digital signal has a respective plurality of states, and further comprising RF detector means for detecting said states of said digital signal and controller means for determining said predetermined value in said counter means in response to said detected states of said digital signal.   
     
     
        .Iaddend. .Iadd.29.  The circuit of claim 26; further comprising controller means for determining said predetermined value in said counter means and error correction means for detecting errors in the reproduced digital signal and supplying signals to said controller means to vary said predetermined value in response to errors in said digital signal. .Iaddend. .Iadd.30. The circuit of claim 26; wherein said apparatus for reproducing includes a rotational speed control circuit responsive to said second window signals supplied by said counter means for operating said apparatus at a predetermined speed for reproducing said digital signal. .Iaddend. .Iadd.31. The circuit of claim 30; wherein said rotational speed control circuit includes operating speed control means for effecting changes in said predetermined speed of said apparatus, and said second window signals from said counter means selectively actuate said speed control means. .Iaddend.