High electron mobility single heterojunction semiconductor devices

Abstract

A thin electron accumulation layer is generated along a heterojunction between two kinds of semiconductors each of which has a different electron affinity. This electron accumulation layer suffers less ionized-impurity scattering, because the thickness does not exceed the spread of an electron wave. A channel constituted with this electron accumulation enjoys an excellent electron mobility, particularly at cryogenic temperatures. A layer configuration fabricated with two different semiconductors having different electron mobilities and a similar crystal lattice coefficient, and including a single heterojunction, is effective to improve electron mobility. Such a layer configuration can be employed for production of an active semiconductor device with high electron mobility, resulting in high switching speed. The semiconductor devices including a FET, a CCD, etc., exhibit an excellent transfer conductance Gm.

I claim: 
     
       1. An active semiconductor device with high electron mobility, comprising a source layer of a semiconductor doped with donor impurities,   a channel layer of a semiconductor having a larger electron affinity than the semiconductor of the source layer and forming a heterojunction with said source layer, wherein a channel is formed in said channel layer along said heterojunction,   at least one control terminal formed on .[.a selected one of.]. said source .[.and channel layers.]. .Iadd.layer .Iaddend.over .[.said.]. .Iadd.a .Iaddend.portion of said heterojunction,   a pair of output terminals selectively formed on said source and channel layers, on opposite sides of said at least one control terminal,   said source layer having sufficiently small thickness, at least under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control electrode,   wherein said output terminals are electrically connected, at least under said at least one control terminal, only by an accumulation of electrons with high mobility in said channel in said channel layer, depending on a control voltage applied to said control terminal.   
     
     
       2. The device of claim 1, said .Iadd.at least one .Iaddend.control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, such that said device is of the normally ON type. 
     
     
       3. The device of claim 1, said .Iadd.at least one .Iaddend.control .[.electrode.]. .Iadd.terminal .Iaddend.being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, such that said device is of the normally OFF type. 
     
     
       4. The device of claim 3, the difference between said electron affinities of said source and channel layers being less than approximately the height of the potential barrier that would form at the bottom of the conduction band in said source layer at the boundary of said at least one .[.the.]. control .[.electrode.]. .Iadd.terminal.Iaddend., if said source layer were sufficiently thick to have a flat portion in its conduction band. 
     
     
       5. The device of claim 1, wherein said at least one control terminal is formed on said source layer and said source layer has a thickness, under said at least one control terminal, equal to or less than approximately ##EQU10## wherein ε S  is the dielectric constant of said source layer, N D  is the concentration of said donor impurities in said source layer,   V D1  is the height of the potential barrier that would form in said source layer at the boundary of said at least one control terminal, if said source layer was sufficiently thick to have a flat portion in its conduction band,   V D2  is the height of the potential barrier that would form in the conduction band in said source layer adjacent said channel layer, if said source layer was sufficiently thick to have said flat portion, and   k is Boltzmann's constant, q is the electron charge, and   T is absolute temperature.   
     
     
       6. The device of claim 5, said source layer being thicker, under said at least one control .[.electrode.]. .Iadd.terminal.Iaddend., than approximately the first term in the formula of claim 5. 
     
     
       7. The device of claim 5, said source layer having a thickness, under said at least one control terminal, that is equal to or less than approximately the first term in the formula of claim 5. 
     
     
       8. The device of claim 7, wherein V D1  >V D2 . 
     
     
       9. The device of claim 7, wherein VD 1  <V D2 . .[. 
     
     
       10.  The device of claim 1, wherein said at least one control terminal is formed on said channel layer, and said source layer has a thickness, under said at least one control terminal, that is equal to or less than.]. ##EQU11## .[.wherein ε SA  is the dielectric constant of said source layer,   N D  is the concentration of said donor impurities in said source layer,   V D  is the height of the potential barrier that would form in the conduction band of the source layer adjacent said channel layer, if the source layer was sufficiently thick that the bottom of its conduction band had a flat portion, and   k is the Boltzmann constant, q is the electron charge, and T is the absolute temperature..]. .[.   
     
     
       11.  The device of claim 10, wherein the ratio of the thickness of said channel layer to the thickness of said source layer, under said at least one control terminal, is greater than approximately.]. ##EQU12## .[.wherein V S  is the height of the potential barrier in the bottom of the conduction band in said channel layer adjacent said at least one control terminal and the Fermi level in said channel,   ΔE C  is the difference in the electron affinities of the source and channel layers,   E F  is the energy difference between the Fermi level and the bottom of the conduction band in the channel layer along said heterojunction, and   ε SG  is the dielectric constant of said channel layer..]. .[.   
     
     
       12.  The device of claim 10, wherein the ratio of the thickness of said channel layer to the thickness of said source layer, under said at least one control terminal, is equal to or less than approximately.]. ##EQU13## .[.wherein V S  is the height of the potential barrier in the bottom of the conduction band in said channel layer adjacent said at least one control terminal and the Fermi level in said channel,   ΔE C  is the difference in the electron affinities of the source and channel layers,   E F  is the energy difference between the Fermi level and the bottom of the conduction band in the channel layer along said heterojunction, and   ε SG  is the dielectric constant of said channel layer..]. .[.   
     
     
       13.  The device of claim 12, said source and channel layers having thicknesses, under said at least one control terminal, such that said device is of the normally ON type..]. .[.14. The device of claim 12, said source and channel layers having thicknesses, at least under said at least one control terminal, such that said device is of the normally OFF 
     
     
        type..]. 15. The device of any one of claims .[.1-14.]. .Iadd.1-9.Iaddend., wherein the non-selected one of said semiconductor layers is grown on a substrate of a substantially non-conductive material. .[.16. The device of claim 11, 12, 13 or 14 wherein said source layer is formed on a buffer layer of an undoped semiconductor, and said buffer layer is formed on a substrate of a substantially non-conductive 
     
     
        material..]. 17. The device of any one of claims .[.1-14.]. .Iadd.1-9.Iaddend., wherein said source and channel layers, and control and output electrodes, comprise a FET having a substantially linear transfer conductance and amplification characteristic as a result of said output electrodes being connected, under said at least one control electrode, only by said high mobility electrons in said channels. .Iadd.18. An active semiconductor device as recited in claim 1, wherein: the source layer is formed of AlGaAs semiconductor material; and   the channel layer is formed of GaAs semiconductor material. .Iaddend. .Iadd.19. An active semiconductor device as recited in claim 1, wherein:   the source layer is formed of AlGaAs semiconductor material; and   the channel layer is formed of Ge semiconductor material. .Iaddend.   
     
     
        .Iadd.  .  An active semiconductor device as recited in claim 1, wherein: the source layer is formed of GaAs semiconductor material; and   the channel layer is formed of Ge semiconductor material. .Iaddend. .Iadd.21. An active semiconductor device as recited in claim 1, wherein:   the source layer is formed of CdTe semiconductor material; and   the channel layer is formed of InSb semiconductor material. .Iaddend. .Iadd.22. An active semiconductor device as recited in claim 1, wherein:   the source layer is formed of GaSb semiconductor material; and   the channel layer is formed of InAs semiconductor material. .Iaddend. .Iadd.23. An active semiconductor device as recited in claim 1, wherein:   said source layer is formed of an n-doped semiconductor material. .Iaddend. .Iadd.24. An active semiconductor device as recited in claim 23, wherein:   said channel layer is selectively formed of an undoped or an unintentionally doped semiconductor material. .Iaddend. .Iadd.25. An active semiconductor device as recited in claim 23, wherein said channel   
     
     
        layer is undoped. .Iaddend. .Iadd.26.  An active semiconductor device as recited in claim 1, further comprising a substrate, said channel layer being formed on said substrate and said source layer being formed on said channel layer, in succession. .Iaddend. .Iadd.27. An active semiconductor device as recited in claim 26, wherein: said substrate is formed of a semi-insulating material. .Iaddend. .Iadd.28. An active semiconductor device as recited in claim 2 or 6, wherein:   said source layer is limited in lateral extent, in a plane transverse to the thickness thereof, substantially to the corresponding lateral extent of said at least one control terminal; and   said pair of output terminals is formed on said channel layer, on opposite sides of said source layer and said at least one control terminal formed thereon. .Iaddend. .Iadd.29. An active semiconductor device as recited in claim 2 or 6, wherein:   a single control terminal is formed on said source layer;   said source layer is limited in lateral extent, in a plane transverse to the thickness thereof, substantially to the corresponding lateral extent of said control terminal; and   said pair of output terminals is formed on said channel layer, on opposite sides of said source layer and said control terminal formed thereon.   
     
     
        .Iaddend. .Iadd.30.  An active semiconductor device as recited in claim 3 or 7, wherein: said source layer, in a plane transverse to the thickness thereof, is substantially coextensive with said channel layer; and   said source layer, in a central portion thereof under said at least one control terminal has said thickness such that said device is of the normally OFF type and the remaining portions of said source layer have a greater thickness, thereby to define a recessed said central portion of said source layer; and   said at least one control terminal is formed on said recessed central portion. .Iaddend. .Iadd.31. An active semiconductor device as recited in claim 30, wherein:   said pair of output terminals is formed on said source layer on said greater thickness portions thereof on opposite sides of said recessed central portion thereof and comprise respective, deeply doped regions of said greater thickness portions of said source layer and the corresponding underlying portions of said channel layer. .Iaddend. .Iadd.32. An active semiconductor device as recited in claim 3 or 7, wherein:   a single control terminal is formed on said source layer;   said source layer, in a plane transverse to the thickness thereof, is substantially coextensive with said channel layer; and   said source layer, in a central portion thereof under said single control terminal, has said thickness such that said device is of the normally OFF type and the remaining portions of said source layer have a greater thickness, thereby to define a recessed, said central portion of said source layer on which said single control terminal is formed. .Iaddend.   
     
     
        .Iadd.33.  An active semiconductor device as recited in claim 32, wherein: said pair of output terminals is formed on said source layer on said greater thickness portions thereof on opposite sides of said recessed central portion thereof and comprise respective, deeply doped regions of said greater thickness portions of said source layer and the corresponding underlying portions of said channel layer. .Iaddend. .Iadd.34. An active semiconductor device as recited in claim 1, said at least one control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. .Iaddend. .Iadd.35. An active semiconductor device as recited in claim 1, a single said control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. .Iaddend. .Iadd.36. An active semiconductor device as recited in claim 1, said source layer having a recess in a central portion thereof, on which said at least one control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device.   
     
     
        .Iaddend. .Iadd.37.  An active semiconductor device as recited in claim 1, said source layer having a recess in a central portion thereof on which a single said control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device. .Iaddend. .Iadd.38. An active semiconductor device as recited in claim 1, said source layer having a central portion of said sufficiently small thickness and remaining portions of greater than said sufficiently small thickness thereby to define a recessed said central portion, and said at least one control terminal being formed on said recessed central portion of said source layer. .Iaddend. .Iadd.39. An active semiconductor device as recited in claim 38, said source layer being limited in lateral extent, in a direction transverse to the thickness thereof, to the spacing between said pair of output terminals; and said output terminals being formed on said channel layer. .Iaddend. .Iadd.40. An active semiconductor device as recited in claim 38, said output terminals being formed on said source layer on opposite sides of said recessed central portion and said at least one control terminal   
     
     
        formed thereon. .Iaddend. .Iadd.41.  An active semiconductor device with high electron mobility, comprising: a substrate;   a channel layer formed on said substrate;   a source layer of a semiconductor doped with donor impurities, formed on said channel layer;   said channel layer comprising a semiconductor having a larger electron affinity than the semiconductor of the source layer and forming a heterojunction with said source layer;   at least one control terminal formed on said source layer and over at least a portion of said heterojunction;   a pair of output terminals each, independently, conductivity connected to said heterojunction and respectively disposed on opposite sides of said at least one control terminal, said source layer having sufficiently small thickness, at least under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control electrode; and   said output terminals being electrically connected, at least under said at least one control terminal, only by an accumulation of electrons with high mobility in a channel defined by said heterojunction, depending on a control voltage applied to said control terminal. .Iaddend. .Iadd.42. An active semiconductor device as recited in claim 41, said source layer having a central portion of said sufficiently small thickness and remaining portions of greater than said sufficiently small thickness thereby to define a recessed said central portion, and said at least one control terminal being formed on said recessed central portion of said   
     
     
        source layer. .Iaddend. .Iadd.43.  An active semiconductor device as recited in claim 41, said source layer being limited in lateral extent, in a direction transverse to the thickness thereof, to the spacing between said pair of output terminals; and said output terminals being formed on said channel layer. .Iaddend. .Iadd.44. An active semiconductor device as recited in claim 41, said output terminals being formed on said source layer on opposite sides of said recessed central portion and said at least one control terminal formed thereon. .Iaddend. .Iadd.45. An active semiconductor device as recited in claim 41, 42, 43 or 44, said at least one control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. .Iaddend. .Iadd.46. An active semiconductor device as recited in claim 41, 42, 43 or 44, said source layer having a recess in a central portion thereof, on which said at least one control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device. .Iaddend.