Synchronization system for digital data

Abstract

A digital signal synchronization system including a digital signal source for supplying an input digital signal, and a plurality of substantially identical integrating circuits, each connected to the digital signal source for integrating the signal for a predetermined time. A plurality of clock sources are also provided, each connected to a corresponding one of the integrating circuits, so that each integrating circuit begins integrating the digital signal at a different time. Decision circuits are connected to the output of each of the integrating circuits for electing one of the integrating circuits according to a predetermined criteria.

What is claimed is: 
     
       1. A digital signal synchronization system comprising: a signal source for supplying an input signal;   an analog to digital converter having an input connected to said signal source; and an output;   a plurality of substantially identical .[.summing circuits.]. .Iadd.integrators, .Iaddend.each connected to said output of said analog to digital converter for summing a plurality of successive signals for a predetermined time;   a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said 171 summing circuits.]. .Iadd.integrators .Iaddend.so that each .[.summing circuit.]. .Iadd.integrator .Iaddend.begins summing said digital signal beginning at a different time; .[.and.].   .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of an output of the associated integrator;   a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend.   decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria, so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.   
     
     
       2. A system as defined in claim 1, wherein said decision means functions to select said one of said summing circuits having the output with the greatest absolute value. 
     
     
       3. A system as defined in claim 1, wherein said summing circuits comprises an adder and a shifter register memory. 
     
     
       4. A system as defined in claim 1, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal. 
     
     
       5. A system as defined in claim 1, wherein each of said clock sources has a different phase. 
     
     
       6. A digital signal synchronization system comprising: a signal source for supplying an input signal;   an analog to digital converter having an input connected to said signal source; and an output;   a plurality of substantially identical summing circuits.Iadd., .Iaddend.each connected to said output of said analog to digital convertor for summing a plurality of successive signals for a predetermined time;   a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time;   decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal; and   .Iadd.each of .Iaddend.said summing circuits .[.comprise.]. .Iadd.comprises .Iaddend.an adder and a shift register memory, .Iadd.and said shift register memory stores a plurality of words, each of said words being representative of the output of the associated adder.Iaddend..   
     
     
       7. A system as defined in claim 6, wherein said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal. 
     
     
       8. A system as defined in claim 6, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal. 
     
     
       9. A system as defined in claim 6, wherein each of said clock sources has a different phase. 
     
     
       10. A digital signal synchronization system comprising: a digital signal source for supplying an input digital signal;   a plurality of substantially identical integrating circuits.Iadd., .Iaddend.each connected to said digital signal source for integrating the signal for a predetermined time;   a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said integrating circuits so that each integrating circuit begins integrating said digital signal at a different time; and   .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of the output of the integrator;   a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend.   decision means connected to the output of each of said 171 integrating.]. .Iadd.summing .Iaddend.circuits for selecting one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits .Iadd.and its associated integrating circuit .Iaddend.such that said clock signal associated with said one of said integrating circuits is the synchronized clock signal associated with said input digital signal.   
     
     
       11. A system as defined in claim 10, wherein said decision means functions to select said one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits having the output with the greatest absolute value. 
     
     
       12. A system as defined in claim 10, when said integrating circuits comprises integrate and dump matched filters. 
     
     
       13. A system as defined in claim 10, wherein each of said clock sources has a frequency identical with the data rate of the input digital signal. 
     
     
       14. A system as defined in claim 10, wherein each of said clock sources has a different phase. 
     
     
       15. A system as defined in claim 10, further comprising convolving means connected to the output of said selected one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits for computing a convolution function signal using the output signal on said output. 
     
     
       16. A system as defined in claim 10, further comprising threshold detection means connected to the output of said selected one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits for sensing the output signal on said output and producing an activating signal if the magnitude of said output signal exceeds a predetermined threshold signal magnitude. 
     
     
       17. A system as defined in claim 10, wherein said .[.integrating circuit comprises a serial.]. memory .Iadd.is .Iaddend.for storing a plurality of words in information representing the successive integrations of said input signal.