Period and frequency measuring instrument

Abstract

A device for determining with high accuracy the period and frequency of an input signal by taking into account the fractions of a clock signal that are normally ignored. A gate signal with an integral number of clock pulses is generated. Each fractional time is accurately measured by first and second integrators, and an up-down counter provides the difference between the fractional times for the final determination.

What is claimed is: 
     
       1. An instrument for determining the period and frequency of an input signal, comprising clock means for providing first and second clock signals, first divider means for dividing said input signal by a predetermined division factor to output a divided signal having a minimum period, wherein a first fractional time is defined between a first output of said first divider means and the first clock pulse of said first clock signal thereafter, and a second fractional time is defined between the following output of said first divider means and the first clock pulse of said first clock .[.means.]. .Iadd.signal .Iaddend.thereafter,   gate signal generating means for generating a gate signal synchronized with said first clock signal,   counter means for counting the clock pulses of said first clock signal during said gate signal,   expansion means for expanding each said fractional time, at least the expanded first fractional time being shorter than the minimum period of said divided signal, .Iadd.less said first fractional time.Iaddend.,   up-down counter means .Iadd.for counting said second clock pulses during the expanded first fractional time, and for counting in the opposite sense said second clock pulses during the expanded second fractional time, .Iaddend.for providing a count .[.of the clock pulses of said second clock signal.]. corresponding to the difference between the first and second expanded fractional times, and   calculator means for calculating the period and frequency of said input signal by adding the count from said counter means to a value corresponding to the count from the up-down counter means.   
     
     
       2. The instrument of claim 1, comprising said expansion means including a first integrator for integrating a first voltage level with a first time constant during a period of time equal to each said fractional time plus a predetermined integral number of clock pulses of the first clock signal, and a second integrator for integrating a second voltage level with a second time constant for each respective expanded fractional time to obtain an integrated value that is the same as each respective final integrated value of the first voltage level,   wherein the first and second voltage levels and time constants are selected to provide, for each said fractional time, smaller slope in time for the absolute value of the integrated value of the second voltage level than for the slope of the absolute value of the integrated value of the first voltage level.   
     
     
       3. The instrument of claim 1, said up-down means counter up-counting the clock pulses of said second clock signal during the expanded first fractional time and down-counting the clock pulses of said second clock signal during the expanded second fractional time. 
     
     
       4. The instrument of claim 2, comprising said first and second clock signals having periods T 01  and T 02 , respectively, said first and second voltage levels being V 1  and V 2 , respectively,   said first and second time constants being R 1  C 1  and R 2  C 2  corresponding to respective resistance and capacitive elements of said first and second integrators, respectively,   said division factor of said divider means being 1/M, wherein M is an integer larger than one,   said counter means counting N of said clock pulses of said first clock signal during said gate signal, and   said up-down counter means up-counting n 1  of said second clock pulses during the expanded first fractional time and down-counting n 2  of said second clock pulses during the expanded second fractional time,   wherein the period P and frequency F of said input signal are calculated by said calculator means as:   P=(T.sub.01 /M)[N+(T.sub.02 V.sub.2 R.sub.1 C.sub.1 /T.sub.01 V.sub.1 R.sub.2 C.sub.2)(n.sub.1 -n.sub.2)]     and its inverse, respectively.     
     
     
       5. The instrument of claim 4, said second clock signal being the same as said first clock signal. 
     
     
       6. The instrument of claim 1, 2, 3, 4 or 5 said minimum period of the output of the first divider means being equal to or longer than each respective sum of any one of said fractional times, plus said predetermined number of clock pulses of the first clock signal, plus the respective expanded fractional time. .Iadd. 
     
     
       7.  A device for determining a number corresponding to the period between first and second input pulses, comprising clock means for providing at least a first clock signal of first clock pulses with which said number corresponding to the period is to be determined, whereby a first fractional time is defined by the time between said first input pulse and the nth of said first clock pulses after said first input pulse, where n is a predetermined integer greater than zero, and a second fractional time is defined by the time between said second pulse and the nth of said first clock pulses after said second input pulse,   a gate signal generator for generating a gate signal synchronized with respective ones of said first clock pulses, said gate signal having a period equal to a predetermined number of periods of said first clock signal,   first counter means for counting said first clock signal during said gate signal,   first integrator means including a first capacitor for integrating a respective reference signal with a respective time constant during said first fractional time, and subsequently during said second fractional time, and for providing a respective output after each of the integrations,   second integrator means including a second capacitor for integrating a respective reference voltage with a respective time constant after each said integration of the first integrator means, and for providing a respective output value is equal to the respective integrated value of said first integrator means,   comprising comparator means for comparing said output of said first and second integrator means, for providing a corresponding output when they become equal,   up-down counter means for being counted up by clock signal corresponding to said first clock signal during the integration by said second integrator means corresponding to said first fractional time, and for being counted down by said clock signal during the integration by said second integrator means corresponding to said second fractional time, and   calculation means for determining a number corresponding to said period between said first and second input pulses from counts of said first and up-down counter means,   wherein each of said up and down counting by said up-down counter means is terminated by a signal corresponding to the output of said comparator means..Iaddend. .Iadd.   
     
     
       8.  The device of claim 7, comprising a first divider for dividing a repetitive external signal by a predetermined integer for providing as a respective output said first and second input pulses..Iaddend. .Iadd.9. The device of claim 8, comprising a first flip-flop to which the output of said divider is provided, said first flip-flop having an output Q which initiates the integration by said first integration means during said first fractional time,   a second divider having as an input said first clock signal gated by said output Q of said first flip-flop, wherein said second divider determines said predetermined integer number n for said first and second fractional time, and having a corresponding output,   a second flip-flop having as an input said output of said further divider and providing a respective Q output for ending such said integration of said first integrator means and initiating the respective integration of said second integrator means,   a third flip-flop, included in said gate signal generator and controlled by said Q output of said second flip-flop for providing as a respective Q output said synchronized gate signal, and   the output of said comparator determines the end of each integration of said second integrator means..Iaddend. .Iadd.10. The device of claim 9, wherein the first gate signal plus said fractional time less said second fractional time determines the period between said first and second input pulses..Iaddend.