Apparatus for analyzing semiconductor memories

Abstract

.[.The disclosure is of.]. .Iadd.An .Iaddend.apparatus for generating raster scans on an oscilloscope combined with an electron microscope used for scanning and examining semiconductor devices. A scanning electron microscope can be operated to generate artificial or induced faults in semiconductor memories, and the raster scanner, in carrying out a scan, will visually display on the oscilloscope natural and artificial or induced faulty locations or cells in semiconductor memories. The semiconductor memory under test is positioned at different locations in the microscope, at each of which an artificial fault is generated until a position is reached, at which the artificial fault coincides, or nearly coincides, with the natural fault location as displayed by the raster scanner. When this is achieved, the electron microscope can then be used to examine the naturally faulty location or cell to determine the reason for the fault.

What is claimed is: 
     
       1. The method of physically locating and optically examining faulty cells in a semiconductor device by means of a scanning electron microscope comprising the steps of positioning a semiconductor module, including a matrix of cells, at a first viewing position in a scanning electron microscope,   electrically scanning and addressing and charging each cell in the semiconductor module and displaying on an oscilloscope the scanned raster of cells and a first faulty cell therein,   including a fault in a second cell in said module by means of the electron beam of said scanning electron microscope,   electrically scanning and addressing each cell in said module and displaying said first and second faulty cells on the oscilloscope,   mechanically moving said module in said microscope to a second position which tends to place the point of impingement of the electron beam of said microscope either on or closer to the location of said first faulty cell and inducing a fault in a third cell,   electrically scanning and addressing each cell in the semiconductor module and displaying on an oscilloscope the scanned raster and said first and third faulty cells therein,   whereby, if said first and third faulty cells coincide in position or are suitably close together as shown by the raster scan on said oscilloscope, then the operator of the microscope can visually inspect the first faulty cell to determine the reason for its being faulty. .Iadd.   
     
     
       2.  A method of physically locating and examining a faulty memory cell in a semiconductor device which contains a matrix of cells, including the steps of: placing said semiconductor device at a first position on a support means;   inducing an artificial fault in a cell, other than said faulty cell, in said device by directing an energy carrying beam at said device which produces electron-hole pairs at the point of impingement;   displaying a pattern which depicts the physical position of the cells in said memory, and indicating on said pattern the position of said faulty cell and said cell at said point of impingement with said induced fault;   moving the point of impingement of said beam closer to the location of said faulty cell and inducing another artificial fault in a cell at the new point of impingement;   redisplaying said pattern and indicating thereon the position of said faulty cell and said cell at the new point of impingement; and   utilizing said beam, if said faulty cell and said cell with said artificial fault coincide in position or are suitably close together as shown by said display, to visually inspect the faulty cell. .Iaddend. .Iadd.   
     
     
       3.  A method of physically locating and examining a faulty memory cell that stores erroneous data in a semiconductor device which contains a plurality of cells, including the steps of: impinging an energy carrying beam on a first cell in said device, other than said faulty cell, which produces electron-hole pairs at the point of impingement and thereby induces erroneous data in said first cell;   sensing that both said faulty cell and said first cell store erroneous data;   displaying the physical positions of the cells with said erroneous data relative to one another; and   utilizing said beam, if the position of said cell with the induced error relative to said faulty cell is suitably close as shown by said display, to visually inspect said faulty cell. .Iaddend. .Iadd.4. A method according to claim 3 and further including the step impinging said beam on another cell, and repeating said sensing and displaying steps until the position of the cell with the induced error is suitably close to said   
     
     
        faulty cell. .Iaddend. .Iadd.5.  Apparatus for physically locating and examining a faulty memory cell in a semiconductor device which contains a matrix of cells, comprising: a means for supporting said semiconductor device;   a means for inducing an artificial fault in a cell, other than said faulty cell, in said device by directing an energy carrying beam at said device which produces electron-hole pairs at the point of impingement;   a fault sensing means, coupled to said semiconductor device while said energy carrying beam is impinging upon it, for sensing the position of the cell with said induced artificial fault;   a display means coupled to said fault sensing means, for displaying a pattern which depicts the physical position of the cells in said memory, and for indicating on said pattern the position of said faulty cell and the cell with said induced fault;   a means for moving the point of impingement of said beam while said fault sensing means and display means are operating, whereby said beam can be directed onto said faulty cell by moving said beam until the position of said cell with said induced fault and said faulty cell as displayed on said display means coincide; and   a means for utilizing said beam to visually display the cell on which said   
     
     
        beam impinges. .Iaddend. .Iadd.6.  Apparatus for physically locating and examining a faulty memory cell that stores erroneous data in a semiconductor device which contains a plurality of cells, comprising: means for impinging an energy carrying beam on any selectable cell in said device to produce electron-hole pairs at the point of impingement and thereby induce erroneous data in said selectable cell;   fault sensing means, coupled to said semiconductor device while said beam is impinging on it, for sensing that both said faulty cell and said selectable cell store erroneous data;   display means, coupled to said fault sensing means, for displaying a graphic representation of the physical positions of said cells with said erroneous data relative to one another; whereby said beam can be directed onto said faulty cell by moving the point at which said beam impinges until the positions of said selectable cell and said faulty cell as shown by said display means coincide; and   means for utilizing said beam to produce an image of the cell on which said beam impinges. .Iaddend. .Iadd.7. A method of physically locating and examining a faulty memory cell that stores erroneous data in a semiconductor device which contains a plurality of cells, comprising:   impinging an energy carrying beam on any selectable cell in said device to produce electron-hole pairs at the point of impingement and thereby induce erroneous data in said selectable cell;   sensing, while said beam is impinging on said semiconductor device, that both said faulty cell and said selectable cell store erroneous data;   displaying a graphic representation of the physical positions of said cells with said erroneous data relative to one another;   moving the point at which said beam impinges until the positions of said selectable cell and said faulty cell as shown by said display means coincide; and   utilizing said beam to produce an image of the cell on which said beam impinges. .Iaddend.