Color television receiver comprising at least one integrated circuit for the luminance signal and the chrominance signals

Abstract

A color television receiver is provided having a fully digital color demodulator wherein the luminance signal and the chrominance signals are separated and digitally processed prior to being converted to analog signals.

What is claimed is: 
     
       1. A color-television receiver, comprising: at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit including a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix and an R-G-B matrix, said chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals, the first of which   has four times the chrominance-subcarrier frequency, and the second to fourth of which have the chrominance-subcarrier frequency with the first and second clock signals having a mark-to-space ratio of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);   an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal at those instants where the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;   a first binary arithmetic stage which multiples the output signal of the analog-to-digital converter by a binary overall-contrast control signal;   a two-stage delay line which delays the output signal of the first binary arithmetic stage by T/2;   a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage;   a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;   a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage and whose enable input is fed with the third clock signal;   a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement while their clock inputs are fed with the fourth clock signal;   a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement;   a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference obtained by two;   a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; and   a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages, the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix, each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube.   
     
     
       2. A color-television receiver as claimed in claim 1, wherein the square-wave clock generator generates, in addition, a fifth and a sixth clock signal which are formed from the third clock signal and the fourth clock signal respectively, by eliminating every second pulse of each period, the buffer-memory arrangement consists of two buffer memories which are operated in parallel at their inputs, and whose enable inputs are fed with the fifth clock signal and the sixth clock signal, respectively, the shift-register arrangement consists of two shift-register subarrangements each of which has n parallel shift registers providing a delay of one line period, the series inputs of the first shift-register subarrangement are connected to the outputs of the first buffer memory, and the clock inputs of this subarrangement are fed with the sixth clock signal, the serial inputs of the second shift-register subarrangement are connected to the outputs of the second buffer memory, and the clock inputs of this subarrangement are fed with the fifth clock signal, the fourth binary arithmetic stage forms the means of the input signals and the output signals of the second shift-register subarrangement, and the fifth binary arithmetic stage subtracts the input signals of the first shift-register subarrangement from the output signals of this subarrangement. 
     
     
       3. A color-television receiver as claimed in claim 1 incorporating R-G-B control of the picture tube, wherein the three digital-to-analog converters associated with the binary R-G-B matrix are fed with a binary color-saturation control signal and the three digital-to-analog converters are fed with a binary brightness control signal. 
     
     
       4. A color-television receiver as claimed in claim 1 and incorporating color-difference control of the picture tube wherein the digital-to-analog converter associated with the second binary arithmetic stage is fed with a binary brightness control signal and the other three digital-to-analog converters are fed with a binary color-saturation control signal. 
     
     
       5. A color-television receiver as claimed in claim 1 and incorporating color-difference control of the picture tube wherein an eighth binary arithmetic stage multiplying the output signal of the third binary arithmetic stage by a binary color-saturation control signal is connected between the outputs of the third binary arithmetic stage and the parallel inputs of the buffer-memory arrangement. 
     
     
       6. A color-television receiver, comprising: at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit including a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix, said chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals, the first of which has four times the chrominance-subcarrier frequency, and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a mark-to-space ratio of 0.5, and the third and fourth clock signal each consisting of two consecutive, T/2 long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);   an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal at those instants where the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;   a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal;   a two-state delay line which delays the output signal of the first binary arithmetic stage by T/2;   a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage;   a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;   a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal;   a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement while their clock inputs are fed with the fourth clock signal;   a fourth binary arithmetic stage which forms the arithmetic mean of the input and the output signals of the shift-register arrangement;   a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference obtained by two;   a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; and   a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages, the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference values of the picture tube.   
     
     
       7. A color-television receiver as claimed in claim 6, wherein the square-wave clock generator generates, an addition, a fifth and a sixth clock signal which are formed from the third clock signal and the fourth clock signal, respectively, by eliminating every second pulse of each period, the buffer-memory arrangement consists of two buffer memories which are operated in parallel at their inputs, and whose enable inputs are fed with the fifth clock signal and the sixth clock signal, respectively, the shift-register arrangement consists of two shift-register subarrangements each of which has n parallel shift registers providing a delay of one line period, the serial inputs of the first shift-register subarrangement are connected to the outputs of the first buffer memory, and the clock inputs of this subarrangement are fed with the sixth clock signal, the serial inputs of the second shift-register subarrangement are connected to the outputs of the second buffer memory, and the clock inputs of this subarrangement are fed with the fifth clock signal, the fourth binary arithmetic stage forms the mean of the input signals and the output signals of the second shift-register subarrangement, and the fifth binary arithmetic stage subtracts the input signals of the first shift-register subarrangement from the output signals of this subarrangement. 
     
     
       8. A color-television receiver as claimed in claim 6 incorporating R-G-B control of the picture tube, wherein an eighth binary arithmetic stage multiplying the output signal of the third binary arithmetic stage by a binary color-saturation control signal is connected between the outputs of the third binary arithmetic stage and the parallel inputs of the buffer-memory arrangement, and the three digital-to-analog converters are fed with a binary brightness control signal. .Iadd. 
     
     
       9.  An arrangement for producing from a composite color analog signal, a plurality of color information digital signals, said arrangement comprising: means responsive to said analog signal for generating first digital signals having a predetermined relationship carried by said composite color analog signals; and   means for processing said first digital signals to generate said color information digital signals, said processing means comprises: means responsive to control signals and to said first digital signals for generating intermediate digital signals; and first processing means for processing said intermediate digital signals to generate said color information digital signals, said first processing means comprises first means for generating first ones of said plurality of color information digital signals by acting on a first set of said intermediate digital signals and a second set of said intermediate digital signals in a predetermined manner, said first set and second successive set of said intermediate digital signals being successive sets of said intermediate digital signals..Iaddend. .Iadd.10. An arrangement in accordance with claim 9, wherein said first means generates said first ones of said plurality of color information digital signals by forming the arithmetic means of said first and second sets of said intermediate digital signals..Iaddend. .Iadd.11. An arrangement in accordance with claim 10, wherein said first ones of said plurality of color information digital   
     
     
        signals represent luminance signal information..Iaddend. .Iadd.12.  An arrangement for producing from a composite color analog signal, a plurality of color information digital signals, said arrangement comprising: means responsive to said analog signal for generating first digital signals having a predetermined relationship to information carried by said composite color analog signals; and   means for processing said first digital signals to generate said color information digital signals, said processing means comprising: first processing means for generating first ones of said color information digital signals in response to said first digital signals, and second processing means for generating other ones of said color information digital signals in response to said first digital signals and said first ones of said color information digital signals..Iaddend. .Iadd.13. An arrangement in accordance with claim 12, wherein said first ones of said color information digital signals represent luminance signals and said other ones of said color information digital signals represent first and second chrominance signals..Iaddend. .Iadd.14. An arrangement in accordance with claim 13, wherein said first digital signal generating means comprises means for generating said first digital signals at a predetermined rate relative to the chrominance subcarrier of said composite color analog signal..Iaddend. .Iadd.15. An arrangement in accordance with claim 14, wherein said predetermined rate is at least twice the frequency of said chrominance subcarrier..Iaddend. .Iadd.16. An arrangement in accordance with claim 15, wherein said first processing means generates said first ones of said color information signals in accordance with the means of the values represented by two successive sets of said first digital signals..Iaddend. .Iadd.17. An arrangement in accordance with claim 16, wherein said second processing means generates said other ones of said color information digital signals by subtracting said first ones of said color information digital signals from said first digital signals..Iaddend. .Iadd.18. An arrangement in accordance with claim 17, comprising means interposed between said digital signal generating means and said processing means for modifying said first   
     
     
        digital signals in accordance with control signals..Iaddend. .Iadd.19.  A circuit arrangement for recovering video color signals from a composite color analog signal, said circuit arrangement comprising: an analog to digital converter having inputs for receiving said composite color analog signal and for forming first digital signals representative of the amplitude of said composite color analog signal at predetermined time intervals at first outputs;   a delay circuit having inputs coupled to said analog to digital converter and first and second outputs;   a first digital circuit having first inputs coupled to said analog to digital converter first outputs and a second input coupled to said delay circuit second output and generating first color information digital signals at first outputs;   a second digital circuit having first inputs coupled to said first digital circuit first outputs and second inputs coupled to said delay circuit first outputs and generating first and second color difference digital signals at outputs..Iaddend. .Iadd.20. A circuit arrangement in accordance with claim 19, comprising a third digital circuit coupled between said analog to digital converter and said delay circuit for receiving said first digital signals from said analog to digital converter, modifying said first digital signals in accordance with control signals and supplying said modified first digital signals to said delay circuit inputs..Iaddend. .Iadd.21. A circuit arrangement in accordance with claim 20, comprising a third digital circuit coupled to the outputs of said second digital circuit, and responsive to said first and second color difference signals for generating a third color difference signal at outputs..Iaddend. .Iadd.22. A circuit arrangement in accordance with claim 21, comprising: a binary R-G-B matrix having inputs coupled to said first digital circuit output, to said second digital circuit outputs, and to said third digital circuit outputs, for generating R, G and B digital outputs..Iaddend. .Iadd.23. A circuit arrangement in accordance with claim 22, comprising:   digital to analog converter means coupled to said R, G and B digital outputs for generating R, G and B analog signals..Iaddend.