Silicon integrated circuits

Abstract

A dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mess and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.

We claim: 
     
       1. A memory comprising a plurality of memory cells arranged in an array of rows and columns, each memory cell including an access transistor and a storage capacitor serially connected, comprising a monocrystalline silicon chip which is grooved to form a plurality of individual mesas (11) arranged in columns and rows characterized in that   polycrystalline doped silicon (14) fills the grooves (13) and is isolated from the mesas by a dielectric layer (20), a separate access transistor is formed on the surface of each mesa, and a separate storage capacitor is associated with each mesa, one plate of the capacitor being formed by a .Iadd.surface .Iaddend.layer (19) on the sidewall of the mesa and the other plate by the polycrystalline silicon fill (14), and the sidewall layer including a low resistance connection to a source/drain region of the surface access transistor.   
     
     
       2. A memory in accordance with claim 1 in which the layer on the sidewall of the mesa is a layer of conductivity type opposite that of the bulk of the mesa for forming a rectifying junction isolating the layer from the bulk. 
     
     
       3. A memory in accordance with claim 1 in which in each mesa the layer makes low resistance connection to a terminal (16) of the access transistor of the mesa. 
     
     
       4. A memory in accordance with claim 3 in which another terminal (15) of the transistor makes low resistance connection to a bit line conductor (23) which extends along the chip overlying a groove and is electically insulated from the underlying polycrystalline silicon. 
     
     
       5. A semiconductive device comprising a monocrystalline silicon chip which is grooved to form a plurality of mesas (11) whose bulk (12) is of one conductivity type and whose top surface includes at least one semiconductive circuit component characterized in that   the walls of the mesa are coated with a dielectric layer (18) and the grooves are filled with conductive silicon material (14), the walls of the mesa include a layer (19) of conductivity type opposite that of the bulk of the mesa, connections (16, 21 and 15) are provided to the separate layers of opposite conductivity type and to the conductive filling material whereby a plurality of capacitors are formed, each between a connection to the layer and a connection to the fill, for interconnection with the semiconductive circuit components on the top surface of the mesas.   
     
     
       6. A random access memory made up of an array of meory cells arranged in rows and columns and interconnected by word and bit lines, each memory cell comprising an access transistor and a storage capacitor serially connected characterized in that   each memory cell is essentially formed in an individual semiconductive mesa, the individual mesas sharing a common semiconductive support,   each mesa is surrounded in turn by a dielectric layer and conductive material and includes a sidewall layer forming a rectifying junction with the bulk of the mesa, the sidewall layer forming one plate of a storage capacitor, the conductive material forming the other plate of a storage capacitor and the dielectric layer serving as the capacitor dielectric, and   each mesa includes at its top surface an access transistor, the access transistor including one terminal which makes low resistance connection to the surface layer in the mesa and another terminal which makes a low resistance connection to a bit line, and   the bit lines comprise conductive films extending over the filled grooves and electrically isolated from the fill. .Iadd.7. A memory comprising a plurality of memory cells arranged in an array of rows and columns, each memory cell including an access transistor and a storage capacitor serially connected, comprising a monocrystalline silicon chip which is grooved to form a plurality of grooves 13   characterized in that   polycrystalline doped silicon (14) fills the grooves (13) and is isolated from the remainder of the monocrystalline silicon chip by a dielectric layer (20), an access transistor is formed on the surface of the chip, and a storage capacitor is associated with each access transistor, one plate of the capacitor being formed by a layer (19) on the sidewall of the groove and the other plate by the polycrystalline silicon fill (14), and the sidewall layer including a low resistance connection to a source/drain region of the surface access transistor. .Iaddend. .Iadd.8. The device of claim 7 in which the groove is a trench with side walls and a bottom. .Iaddend. .Iadd.9. The device of claim 8 in which the depth of the trench   
     
     
        is greater than the width. .Iaddend. .Iadd.10.  A memory comprising a plurality of memory cells arrange in an array of rows and columns, each memory cell including an access transistor and a storage capacitor serially connected, comprising a monocrystalline silicon chip which is grooved to form a plurality of grooves 13 characterized in that   an electrode 14 extends into a groove and is isolated from the remainder of the silicon chip by a dielectric layer 20, an access transistor is formed on the surface of the chip and a storage capacitor is associated with each access transistor, one plate of the capacitor being formed by a surface layer 19 on the sidewall of the groove and the other by the electrode 14, and a low resistance connection between the storage capacitor and the access transistor. .Iaddend. .Iadd.11. A memory comprising a plurality of memory cells arranged in an array of rows and columns, each memory cell including an access transistor and a storage capacitor serially connected, comprising a monocrystalline silicon chip which is grooved to form a plurality of grooves   characterized in that   the storage capacitor is a parallel plate capacitor with the major plane of the parallel plates extending into one of said grooves. .Iaddend.