Resistive gate FET flip-flop storage cell

Abstract

An improved bistable FET circuit is disclosed which employs a reduced number of device elements and occupies less space in an integrated circuit. The flip-flop circuit includes the FET device having its source connected to a first potential and a second FET device having its source also connected to the first potential. The first FET device has a gate electrode composed of a resistive material with the first side connected to the drain of the second FET device and the second side connected to a second potential. The second FET device has a gate electrode comprised of a resistive material with the first side connected to the drain of the first FET device and a second side connected to the second potential. In this manner, the resistive gate of the first device serves as the load for the second device and the resistive gate of the second device serves as the load for the first device. Application of this circuit to electrically programmable PLA's and to random access memories is disclosed.

I claim: 
     
       1. A flip-flop circuit, comprising: a first FET device having its source connected to a first potential;   a second FET device having its source connected to said first potential;   said first FET device having a gate electrode composed of a resistive material with a first side connected to the drain of said second FET device and a second side connected to a second potential;   said second FET device having a gate electrode composed of a resistive material with a first side connected to the drain of said first FET device and a second side connected to said second potential;   whereby a compact flip-flop circuit is formed.   
     
     
       2. The circuit of claim 1, wherein said resistive material for said gate electrodes of said first and second FET devices is polycrystalline silicon. 
     
     
       3. The flip-flop circuit of claim 1, wherein said gate of said first FET device has a different resistance between said first and second sides than that for said second FET device; whereby the flip-flop will assume a predetermined state when said first and second potentials are turned on.   
     
     
       4. The circuit of claim 3, wherein said resistive material for said gate electrodes of said first and second FET devices is polycrystalline silicon. 
     
     
       5. The circuit of claim 4 wherein said different resistance between said first and second gates is due to a difference in concentration of conductivity enhancing dopants therein. 
     
     
       6. The circuit of claim 4, wherein said different resistances are due to a difference in the mechanical dimensions of said gates. 
     
     
       7. A programmable PLA circuit connected between a bit partitioning input line, a product term line, a ground line and a programming line, comprising: a first and second FET device connected in series between said product term line and said ground line, with the gate of said first FET device connected to said bit partitioning input line, forming a read only memory element;   a third FET device having its source connected to said product term line and its gate connected to said programming line;   a fourth FET device having its source connected to a first potential and its drain connected to the drain of said third FET device;   a fifth FET device having its source connected to said first potential and its drain connected to the gate of said second FET device;   said fourth FET device having a gate electrode composed of a resistive material with a first side connected to the drain of said fifth FET device and a second side connected to a second potential;   said first FET device having a gate electrode composed of a resistive material with a first side connected to the drain of said fourth FET device and a second side connected to said second potential;   whereby the conduction state of said second FET device is controlled by the flip-flop circuit formed by said fourth and fifth FET devices, whose state is set through said third FET device, thereby blocking conduction through said first FET device.   
     
     
       8. The circuit of claim 7, wherein said resistive material for said gate electrodes of said fourth and fifth devices is polycrystalline silicon. 
     
     
       9. A random access memory element connected between a first and second bit/sense lines and a word line, comprising: a first FET isolation device having its source connected to said first bit/sense line and its gate connected to said word line;   a second FET isolation device having its source connected to said second bit/sense line and its gate connected to said word line;   a first FET storage device having its source connected to a first potential and its drain connected to the drain of said first FET isolation device;   a second FET storage device having its source connected to said first potential and its drain connected to the drain of said second FET isolation device;   said FET storage device having a gate electrode composed of a resistive material with a first side connected to the drain of said second FET storage device and a second side connected to a second potential;   said second FET storage device having a gate electrode composed of a resistive material with a first side connected to the drain of said first FET storage device and a second side connected to said second potential;   whereby a compact random access memory array is formed.   
     
     
       10. The memory element of claim 9, wherein said resistive material for said gate electrodes of said first and second FET storage devices is polycrystalline silicon. .Iadd. 
     
     
       11.  A binary switching circuit, comprising: an insulated gate field effect transistor device having its source/drain path connected between a first binary potential and an output node and having a gate electrode;   a load device connected between said output node and a second binary potential;   said gate electrode composed of a resistive material having a first side connected to said second binary potential and a second side connected to a binary signal source selectively inputting either said first binary potential or said second binary potential thereto;   said first binary potential applied to said second side causing a current to flow through said resistive material reducing the potential of portions of said resistive material between said first and second sides to be a magnitude between said first and said second binary potentials, thereby reducing the conductivity of said source/drain path resulting in a first output signal potential at said output node;   said second binary potential applied to said second side causing substantially no current to flow through said resistive material, maintaining the potential of said gate at said second binary potential, thereby increasing the conductivity of said source/drain path resulting in a second output potential at said output node;   whereby said binary signals applied to said second side of said gate produce a binary output signal at said output node.