Solid state digital-to-analog converter

Abstract

A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

I claim: 1. An integrated-circuit digital-to-analog converter comprising: 
     
        resistor..]..]..Baddend. .Badd..[..[.4.  A converter as in claim 1, wherein said substrate is formed with four switching transistors the emitters of which have areas in the ratios of 1:2:4:8..]..]..Baddend. .Badd..[..[.5. Apparatus as in claim 1, wherein said substrate has said plurality of transistors diffused therein to serve as separate current sources corresponding to respective bits of a digital input signal; each of said transistors comprising an emitter, a base and a collector;   the areas of the respective emitters for said transistors differing in   
     
     
        accordance with a binary weighting pattern..]..]..Baddend. .Badd..[..[.6. Apparatus as in claim 5, wherein each of said transistors has a number of separate equal-size emitter sections, with the number of sections in each case being in accordance with said binary weighting pattern..]..]..Baddend. .Badd..[..[.7. Apparatus as in claim 5, wherein the size of the base segment for each transistor is at least approximately proportional to the area of the corresponding emitter..]..]..Baddend. .Badd..[..[.8. Apparatus as in claim 7, wherein said substrate is formed with a single collector segment common to all of said transistors..]..]..Baddend. .Iadd..[..[.9. An integrated-circuit digital-to-analog converter comprising: a plurality of transistors on a single monolithic substrate;   an output line;   switch control means operable by a digital input for selectively activating any of said transistors to pass the current thereof through said output line;   circuit means for said transistors to set different levels of current through each transistor according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the selected transistors represents an analog output corresponding to said digital input;   each of said transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in the activated transistors..]..]..Iaddend. .Iadd..[..[.10. Apparatus as in claim 9, wherein the emitter area of each of said transistors is proportional to the particular current level assigned thereto..]..]..Iaddend. 11. An integrated-circuit digital-to-analog converter comprising:   a .Badd.first .Baddend.plurality of transistors on a single monolithic substrate each adapted to conduct current;   an output line;   .Badd.first .Baddend.means operable by a first part of a digital input signal for developing in said output line a flow of current representing the summation of the currents of any of said .Badd.first .Baddend.transistors selected in accordance with .Badd.said first part of .Baddend.said digital input signal;   circuit means for said .Badd.first .Baddend.transistors to set different levels of current therethrough according to a predetermined weighting pattern such that the sum of the currents produced in said output line by the transistors represents .Iadd..[..[.an.]..]..Iaddend. .Badd.a first .Baddend.analog output signal corresponding to said .Badd.first part of said .Baddend.digital input signal;   each of said .Badd.first .Baddend.transistors being formed to present in said substrate a respective conductive area proportional to the particular current level assigned thereto in accordance with said weighting pattern to provide uniform current density in said transistors. .Badd.;   a second plurality of transistors on a substrate each adapted to conduct current;   said second plurality of transistors being matched to said first plurality of transistors;   second means operable by a second part of said digital input signal for developing in said output line a flow of current representing the summation of the currents of any of said second plurality of transistors selected in accordance with said second part of said digital input signal;   said second means including means to attenuate the current contribution from said second transistor as developed in said output line to provide for proper relative weighting between that current contribution and the contribution of said first transistors;   circuit means for said second transistors to set different levels of current therethrough according to said predetermined weighting pattern, the sum of the currents produced in said output line by said second transistors, after attenuation by said attenuation means, representing an additive supplement to the analog output signal in accordance with said second part of said digital input signal, properly weighted relative to said contribution of said first transistors;   each of said second transistors being formed to present a respective conductive area proportional to the particular current level assigned thereto in accordance with said predetermined weighting pattern to provide a current density in said second transistors which is uniform and equal to   
     
     
        the current density of said first transistors.Baddend.. .Badd.12. A converter as in claim 11, wherein all of said transistors include base, emitter and collector electrodes; the area of each of said transistor emitters being proportional to the magnitude of current therethrough. .Baddend. .Badd.13. A converter as in claim 12, wherein said second transistors are formed on a second substrate different from the substrate carrying said first transistors. .Baddend. .Badd.14. A converter as in claim 12, wherein said first transistors are four in number and carry respective currents in the ratio of 8:4:2:1;   said second transistors being four in number and arranged to carry respective currents in the ratio of 8:4:2:1. .Baddend. .Badd.15. A converter as in claim 1, including a second plurality of integrated-circuit transistors at least substantially identical to said first plurality of transistors and operable to produce a second summation current corresponding to a second, lower-order part of said digital input; and   attenuation means coupling said second summation current to said summing means to augment the summation current from said first plurality of transistors by the current from said second plurality of transistors attenuated by a factor corresponding to the relationship between said lower-order digital signal part and the order of the digital signal controlling said first plurality of transistors. .Baddend.