Moderate field hole and electron injection from one interface of MIM or MIS structures

Abstract

A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection from the opposite interface is blocked due to the larger insulator band gap near this interface. A graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure may be fabricated by forming several pyrolytic or CVD SiO 2 layers over a relatively thick thermal SiO 2 layer, with the pyrolytic SiO 2 layers having sequentially increasing excess Si content. This structure may also be fabricated by controlled Si ion implantation in the thermal SiO 2 layer.

We claim: 
     
       1. A metal-insulator-metal or metal-insulator-semiconductor structure .[.wherein the band gap of the insulator layer near one interface only is reduced.]..Iadd.comprising an insulator having a region of reduced band gap disposed near one insulator-metal interface only .Iaddend.to provide an injection region where holes or electrons, depending on voltage bias, can be injected into .[.the.]. .Iadd.said .Iaddend.insulator under moderate electric field conditions from the contact at .[.this.]. .Iadd.said one insulator-metal .Iaddend.interface while, simultaneously, electron or hole injection from the opposite interface is blocked due to the large insulator band gap near .[.this.]. .Iadd.said opposite .Iaddend.interface. .[.2. The structure of claim 1 comprising a silicon substrate having thereon a relatively thick thermal oxide insulator layer and a metal or semiconductor electrical contact on the thermal oxide insulator layer, said thermal oxide having a decreasing band gap in the vicinity of the electrical contact interface, said decreasing band gap being produced by ion implantation..]. .[.3. The structure recited in claim 1 comprising a silicon substrate having a first relatively thick thermal oxide insulator thereon over which is deposited a plurality of relatively thin pyrolytic oxide layers, each successively deposited pyrolytic oxide layer containing an increasing excess silicon content, and a metal or semiconductor contact on the last deposited pyrolytic oxide 
     
     
        layer..]. 4. A graded oxide metal-.Iadd.gate.Iaddend.-silicon dioxide.Iadd.gate-silicon.Iaddend.-silicon 14 substrate .[.MGOS.]. FET structure having an injection region adjacent to .[.the.]. .Iadd.said metal .Iaddend.gate .[.electrode.]., said injection region comprising a 
     
     
        .[.thin.]. .Iadd.region which exhibits a .Iaddend.graded band gap. 5. The .[.MGOS.]. FET structure as recited in claim 4 wherein .[.the.]. .Iadd.said .Iaddend.gate .[.structure.]. .Iadd.insulator .Iaddend.comprises a .[.relatively thick.]. thermal oxide formed on .[.a.]. .Iadd.said .Iaddend.silicon substrate and .Iadd.said injection region comprises .Iaddend.a plurality of .[.relatively thin.]. pyrolytic oxide layers formed over .[.the.]. .Iadd.said .Iaddend.thermal oxide, each successive pyrolytic oxide layer containing an increasing .[.excess.]. silicon content .Iadd.relative to the amount of silicon in the as grown 
     
     
        thermal oxide.Iaddend.. 6. In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions.[., the improvement wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface.]. .Iadd.comprising a region of reduced band gap forming a portion of said insulated gate structure disposed near the interface between the insulator and the gate electrode of said insulated gate structure .Iaddend.to provide an injection region wherein holes or electrons, depending on voltage bias, can be injected into .[.the.]. .Iadd.said .Iaddend.insulator under moderate electric field conditions from .[.the.]. .Iadd.said .Iaddend.gate .[.electrical contact.]. .Iadd.electrode .Iaddend.while, simultaneously, electron or hole injection from the .[.substrate.]. interface .Iadd.between said substrate and said insulator .Iaddend.is blocked due to the large insulator band gap at .[.this.].  .Iadd.said last mentioned 
     
     
        .Iaddend.interface. 7. The MOS FET device of claim 6 wherein .[.the insulator.]. .Iadd.said region of reduced band gap .Iaddend.comprises a .[.thermal oxide.]. .Iadd.region .Iaddend.having a decreasing band gap in the vicinity of the .[.gate electrical contact.]. interface.[., said decreasing band gap being produced by ion implantation.]. .Iadd.between 
     
     
        said gate electrode and said insulator.Iaddend.. 8. The MOS FET device of claim 6 wherein .[.the.]. .Iadd.said .Iaddend.insulator .[.comprises a first relatively thick.]. .Iadd.is a .Iaddend.thermal oxide .[.layer over which is deposited.]. .Iadd.and said region of reduced band gap is .Iaddend.a plurality of .[.relatively thin.]. pyrolytic oxide layers, each successively deposited pyrolytic oxide layer containing .[.an increasing silicon content.]. .Iadd.more silicon than the previously deposited layer and each of said layers containing more silicon than the as grown thermal oxide.Iaddend.. .Iadd.9. A metal-insulator-semiconductor structure comprising a silicon substrate having a thermal oxide insulator thereon over which is deposited at least one relatively thin oxide layer, each successively deposited oxide layer containing more silicon than the previously deposited oxide layer and each of said layers containing more silicon than the as grown thermal oxide insulator, and a metal or semiconductor contact on the last deposited oxide layer. .Iaddend. .Iadd.10. A graded oxide metal gate-silicon dioxide-silicon FET structure comprising a silicon substrate, a gate oxide of silicon dioxide disposed thereon and an injection region adjacent to said metal gate, said injection region comprising at least one relatively thin oxide layer formed over said gate oxide layer, each successive thin oxide layer containing more silicon than the previously formed oxide layer and each of said layers containing more silicon than said gate oxide. .Iaddend. 
     
     
        .Iadd. 1.  In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate of one conductivity type, a pair of spaced apart regions of opposite conductivity type in said substrate and an insulated gate structure disposed between said pair of regions, the improvement wherein the insulator of said insulated gate structure comprises a first layer of silicon oxide over which is deposited at least one relatively thin oxide layer, each successively deposited oxide layer containing more silicon than the previously formed oxide layer and each of said layers containing more silicon than said first layer of silicon oxide. .Iaddend. .Iadd.12. The structure of claim 1 wherein said semiconductor is a silicon substrate, said insulator is a thermal oxide and said region of reduced band gap is a region of said insulator which exhibits a continuously decreasing band gap due to a continuously increasing content of silicon over that contained in the as grown thermal oxide as said region approaches said one insulator-metal interface and, a metal or semiconductor electrical contact disposed on said insulator. .Iaddend. .Iadd.13. The structure recited in claim 1 wherein said semiconductor is a silicon substrate, said insulator is a thermal oxide and said region of reduced band gap is a plurality of deposited pyrolytic oxide layers each successively deposited layer containing more silicon than the previously deposited layer and each of said layers containing more silicon than the as grown thermal oxide, and a metal or semiconductor contact deposited on the last deposited of said pyrolytic oxide layers. .Iaddend. .Iadd.14. A metal-insulator-semiconductor structure comprising a silicon substrate, a silicon oxide insulator disposed on said substrate and at least another silicon oxide layer disposed on said insulator having a silicon content therein in excess of that in said silicon oxide insulator, and a conductive contact on said at least another oxide layer. .Iaddend. .Iadd.15. A metal-insulator-semiconductor structure comprising a substrate of semiconductor material, a first layer of an oxide of said semiconductor material disposed on said substrate, at least another layer of an oxide of said semiconductor material having a semiconductor material content therein in excess of that in said first layer disposed on said first layer to reduce the band gap of said at least another layer, and a conductive contact on said at least another layer. .Iaddend. .Iadd.16. A metal-insulator-semiconductor structure according to claim 15 wherein said semiconductor material is silicon, said first layer of an oxide is silicon dioxide and, said at least another layer of oxide is silicon dioxide having a silicon content therein in excess of that in said first layer. .Iaddend.