Insulated gate field-effect transistor comprising a mesa channel and a thicker surrounding oxide

Abstract

An insulated gate field-effect transistor and a method of making same, in which the channel is provided in a mesa region of a silicon body, and the channel is surrounded by thicker silicon oxide over the adjacent source and drain regions. A thinner insulating layer is over the channel, and a gate electrode on the latter. The manufacturing method involves masking the channel region while growing silicon oxide around it causing the oxide to penetrate into the silicon areas surrounding the channel to provide the channel in a mesa surrounded by the oxide.

What is claimed is: 
     
       1. An insulated gate field-effect transistor comprising a semiconductive body of silicon of one type conductivity having a surface portion comprising a silicon mesa standing a given height above the surface portion and comprising a channel region of said transistor, spaced source and drain regions of the opposite type conductivity adjacent the surface portion and the mesa and on opposite sides of the mesa, a first layer of an insulating material constituted at least in part of silicon oxide on and adherent to the body surface at least at portions overlying the source and drain regions and at adjacent portions of the body surrounding the source, drain and channel regions, the entire interface between said first insulating layer portions and the body lying below .[.tre.]. .Iadd.the .Iaddend.mesa top, a second layer of an insulating material .Iadd.directly .Iaddend.on the top surface of the mesa and adjoining the first insulating layer portions adjacent thereto, each of said insulating layers having a thickness in a direction corresponding to its smallest dimension, the portions of said first insulating layer at least overlying the source and drain regions and the said adjacent portions of the body having a thickness at least equal to the given height of the mesa such that the said insulating layer portions extend to a height in their thickness direction at least equal to that of the mesa and the top surfaces of said first insulating layer portions extend substantially parallel to said surface portion and at the level of or above the mesa top, said second insulating layer having a thickness substantially smaller than that of the first insulating layer portions, a gate electrode having a portion on the second insulating .[.layers.]. .Iadd.layer.Iaddend., a source electrode having a portion on the first insulating layer and electrically connected through an opening therein to the source region, and a drain electrode having a portion on the first insulating layer and electrically connected through an opening therein to the drain region.Iadd., the second insulating layer lying between the gate electrode and the silicon mesa top consisting entirely of silicon oxide.Iaddend.. 
     
     
       2. A transistor as set forth in claim 1 wherein the top surfaces of the first and second insulating layers are substantially at the same level. 
     
     
       3. A transistor as set forth in claim 1 wherein the mesa height is at least 1000 A. 
     
     
       4. A transistor as set forth in claim 1 wherein the first insulating layer is entirely of silicon oxide. .[.5. A transistor as set forth in claim 4 
     
     
        wherein the second insulating layer comprises silicon nitride..]. 6. A transistor as set forth in claim 1 wherein the gate electrode has another portion extending over adjacent thicker first insulating layer portions 
     
     
        and overlapping the source and drain regions. 7. A transistor as set forth in claim 1 wherein the first insulating layer portions overlying the said adjacent body portions surrounding the source, drain and channel regions are thicker than the first insulating layer portions overlying the source and drain regions. .Iadd. 8. An insulated gate field-effect transistor comprising a semiconductive body of silicon of one type conductivity having a surface portion comprising a silicon mesa standing a given height above the surface portion and comprising a channel region of said transistor, spaced source and drain regions of the opposite type conductivity adjacent the surface portion and the mesa and on opposite sides of the mesa, a first layer of an insulating material constituted at least in part of silicon oxide on and adherent to the body surface at least at portions overlying the source and drain regions and at adjacent portions of the body surrounding the source, drain and channel regions, the entire interface between said first insulating layer portions and the body lying below the mesa top, a second layer of an insulating material comprising silicon oxide directly on the top surface of the mesa and adjoining the first insulating layer portions adjacent thereto, each of said insulating layers having a thickness in a direction corresponding to its smallest dimension, the portions of said first insulating layer at least overlying the source and drain regions and the said adjacent portions of the body having a thickness at least equal to the given height of the mesa such that the said insulating layer portions extend to a height in their thickness direction at least equal to that of the mesa and the top surfaces of said first insulating layer portions extend substantially parallel to said surface portion and at the level of or above the mesa top, said second insulating layer having a thickness substantially smaller than that of any of the first insulating layer portions, a gate electrode having a portion on the second insulating layer, the first insulating layer portion overlying the source and drain regions being thinner than the first insulating layer portion surrounding the source, drain and channel regions forming a step where said layer portions adjoin, a source electrode having a portion on the thicker first insulating layer portion and electrically connected through an opening in the first insulating layer to the source region, and a drain electrode having a portion on the thicker first insulating layer portion and electrically connected through an opening in the first insulating layer to the drain region. .Iaddend.