Asynchronous logic array

Abstract

An asynchronous logic array capable of directly implementing Petri net specification of digital systems is disclosed. The array can be used in general synthesis of asynchronous digital circuits and systems. The parallel nature of the array gives the realized systems the speed and other characteristics of hard wired circuits even though they are realized from a uniform logic array. The logic array is particularly suited for implementing control circuits and promises to extend the field of micro programming to asynchronous and parallel computers.

What is claimed is: 
     
       1. A logic array comprising a plurality of groups of column conductors and plurality of groups of row conductors arranged in a substantially orthogonal relationship, each group of column conductors being called a column, each group of row conductors being called a row, and each row and each column is connected by one of at least five types of connections which are characterized as a "dot" connection, a "cross" connection, a "1" connection, a "0" connection and a "null" connection; each column and row being in one of two states, an "ON" state and an "OFF" state;   a row "firing" when every column connected to that row by a "dot" or a "1" connection is "ON" and every column connected to that row by a "0" connection is on "OFF";   means to change the state of the columns in response to "firings" of rows, the said means turning "OFF" columns connected to a "firing" row by a "dot" connection, and said means changing the state of the columns connected to a "firing" row by a "cross" connection;   a plurality of arbiters,   each arbiter being connected to plurality of selected rows,   the rows which are not connected to an arbiter firing independently of another where as those rows connected to an arbiter "fire" in succession and not at the same time;   means for connecting inputs to selected columns to cause the states of the selected columns to be altered in accordance with changes in the state of inputs, means for connecting selected columns to provide outputs where the state of the output is determined by the state of the selected columns. .Iadd.   
     
     
       2.  A logic array comprising: A. a set of substantially parallel row conductors, each of said row conductors having a potential corresponding to a binary state,   B. a set of substantially parallel column conductors, said column conductors being orthogonal to said row conductors,   C. an array of cell networks, each cell network being associated with one of said column conductors and one of said row conductors,   D. column contact means for segmenting at least one of said column conductors into two or more column segments, each of said column conductors having a potential corresponding to a binary state,   E. cell contact means for coupling selected ones of said column segments to selected ones of said row conductors by way of cell networks associated with said selected column and row segments, and   F. at least one storage element, said storage element being associated with and coupled to at least one of said column segments, wherein said storage element includes means for storing a signal representative of the binary state of said one column segment, and includes means for coupling said stored signal to at least one of the row conductors associated with said one column segment. .Iaddend. .Iadd.   
     
     
       3.  The logic array according to claim 2 wherein said storage element is an edge triggered flip-flop. .Iaddend..Iadd. 4. The logic array according to claims 2 or 3 wherein said column contact means, said row contact means and said cell contact means are programmable. .Iaddend. .Iadd. 5. A logic array comprising: A. a set of substantially parallel row conductors, each of said row conductors having a potential corresponding to a binary state,   B. a set of substantially parallel column conductors, said column conductors being orthogonal to said row conductors, each of said column conductors being adapted to have a potential corresponding to a binary state,   C. a plurality of cell networks, each cell network being associated with one of said column conductors and one of said row conductors, and first and second types of associated cell contact means, (i) said first type of contact means being adapted to unidirectionally couple selected ones of said column conductors to selected ones of said row conductors by way of cell networks associated with said selected column and row conductors, and wherein for each row conductor having column conductors coupled to that row by cell networks and said associate cell contact means of said first type, the binary state each of said row conductors is related to the binary state of all of those column conductors, (ii)   said second type of contact means being adapted to unidirectionally couple selected ones of said row conductors to selected ones of said column conductors by way of cell networks associated with said selected column and row conductors, therein for each column conductor having row conductors coupled to that column conductor by cell networks and said associated cell contact means of said second type, the binary state of each of said column conductors is related to the binary state of all of those row conductors and   D. arbiter means, said arbiter means having inputs coupled to at least two of said row conductors having column conductors coupled thereto by way of said cell networks and associated contact means of said first type, and said arbiter means having outputs coupled to at least two of said row conductors having column conductors coupled thereto by way of said cell networks and associated contact means of said second type, wherein the row conductor coupled to each of said outputs is associated with at least one of the row conductors coupled to said inputs, wherein said arbiter means includes means for detecting binary state changes of one or more of said row conductors coupled to said inputs, and in response thereto, changing the binary state of only one of the associated row conductors coupled to said outputs for as long as its associated row conductor coupled to said   
     
     
        input is characterized by said changed state. .Iaddend..Iadd. 6.  A logic array according to claim 5 wherein said arbiter means includes means for detecting a succession of pairs of binary state changes of one or more of said row conductors coupled to said inputs, and in response thereto providing pairs of binary state changes of said associated row conductors coupled to said outputs in a time sequence related to the sequence of said detected pairs of state changes at said inputs. .Iaddend..Iadd. 7. A logic array according to claim 5 wherein said arbiter means includes means for responding to substantially simultaneous state changes on two or more of the row conductors coupled to said inputs by changing the state of said row conductors coupled to said outputs one at a time in a sequence. .Iaddend.