Mass memory access method and apparatus

Abstract

A method and apparatus for transferring digital data between a mass memory and a random access memory. The mass memory has a plurality of memory loops, each having a plurality of memory cells, and a read/write device which either outputs data from the memory cells or inputs data to the memory cells. Each memory cell is identified by an address that specifies its place in the loop sequence starting from a reference cell. A loop position counter is set at zero when the reference cell of the selected memory loop is at the read/write device. The loop position counter is advanced by one count each time the next memory cell in the sequence is moved into operative relationship with the read/write device. Transfer of data between the mass memory and the random access memory is accomplished without any delay under the control of a random access memory address counter which is synchronized with the loop position counter. A transfer counter terminates the data transfer when an entire data loop has been transferred into or out of the mass memory. Since the loop position counter and random access memory address counter are synchronized, the transferred data will be written into the correct memory cells in either memory regardless of which mass memory cell is in operative relationship with the read/write device at the time the data transfer is initiated. Thus, this invention eliminates latency time in the transfer of data between a mass memory and a random access memory.

The principles of this invention having now been fully explained in connection with the foregoing, I hereby claim as my invention: 
     
       1. A method of transferring digital data between a mass memory having a plurality of storage loops and having a loop position counter associated therewith and a random access memory having an address counter associated therewith, each of said storage loops having a capacity to store N bits of digital data, and both of said counters having N steps in their counting cycle, said method comprising the steps of: (A) selecting at least one storage loop in said mass memory which contains the data to be transferred to said random access memory or which is the destination for data to be transferred from said random access memory;   (B) setting said random access address counter to the same state as said loop position counter regardless of which step said loop position counter is at in its counting cycle;   (C) transferring the bit of digital data which corresponds to the current state of both counters from one memory to the other;   (D) advancing both counters by one step in their counting cycle; and   (E) repeating steps (C) and (D) until N bits of digital data have been transferred from one memory to the other. .[.2. Apparatus for transferring digital data between a mass memory having a plurality of storage loops and having a loop position counter associated therewith and a random access memory having an address counter associated therewith, each of said storage loops having a capacity to store N bits of digital data, and both of said counters having N steps in their counting cycle, said apparatus comprising:   a transfer counter having N steps in its counting cycle;   a clock coupled to the clock input of said mass memory and to said loop position counter;   means for generating a READ signal indicating that data is to be read out of said mass memory;   means for generating a WRITE signal indicating that data is to be written into said mass memory;   means for generating a LOOP signal indicating that a loop is to be selected in said mass memory;   means for generating a DATA signal indicating that data is to be transferred between said mass memory and said random access memory;   means for generating a POSITION signal indicating that the output of said loop position counter is to be read;   a one-shot multivibrator having an enable input and a trigger input and an output; and   means for applying a trigger input to said one-shot multivibrator when one of said READ or WRITE signals is true and one of said DATA, LOOP or   
     
     
        POSITION signals is true..]. .[.3.  The apparatus according to claim 2 wherein said mass memory has a READ ENABLE input and a WRITE ENABLE input, and also comprising: means for triggering said READ ENABLE input when said READ and said DATA signals are ture; and   means for triggering said WRITE ENABLE input when said WRITE and said DATA signals are true..]. .[.4. The apparatus according to claim 2 and also comprising:   a two-to-one multiplexer having two signal inputs;   a control input and an output, the output of said multiplexer being coupled to the clock input of said mass memory, one signal input of said multiplexer being coupled to the output of said clock, said trigger input of said one-shot multivibrator being coupled to the other signal input of said multiplexer, and the output of said one-shot multivibrator being coupled to the control input of said multiplexer..]. .Iadd. 5. Apparatus for transferring digital data between a mass memory having a plurality of storage loops, with each storage loop having "N" cells each accepting a data bit; and   having a loop position counter for indicating which cell in said loop is operative to receive or transmit data; and   a random access memory having an address counter therewith having "N" steps in the counting cycle, said apparatus comprising:   a transfer counter means having "N" counting steps in its counting cycle;   first circuit means coupled to said random access memory and to said mass memory for (a) selecting a unique one of said plurality of mass memory loops, (b) determining the cell position in said selected loop, and (c) indicating the data that is to be transferred between said random access memory and said selected loop of said mass memory;   second circuit means coupled to said transfer counter, to said random access memory address counter, and to said first circuit means for resetting said transfer counter and for adjusting said random access memory address counter in accordance with the loop cell position determined by said first circuit means; and   third circuit means coupled to said first circuit means, to said random access memory, and to said mass memory for repetitively (a) advancing the loop position (b) advancing the count of said transfer counter means, and (c) transferring data between said selected loop of said mass memory and said random access memory each time said first circuit means indicates that data is to be transferred between said random access memory and said mass memory until said transfer counter means overflows. .Iaddend..Iadd. 6. The invention according to claim 5, wherein said first circuit means comprises:   data processing means for producing a two bit address word to initiate loop selection and producing a WRITE command to initiate transfer of data from said random access memory indicative of a desired loop to said mass memory;   address decoder means coupled to said data processing means for decoding said two bit address word to produce a LOOP command to initiate transfer of data stored in said random access memory indicative of said selected loop; and   latch means coupled to said random access memory and responsive to LOOP commands from said data processing means for latching said address   
     
     
        indicative of said selected loop to said mass memory. .Iaddend..Iadd. 7. The apparatus according to claim 6, wherein said data processing means further produces a READ command to initiate transfer of data from said mass memory to said random access memory and to said transfer counter, wherein said address decoder decodes said two bit address work to produce POSITION command to initiate examination of said loop counter to ascertain loop position, and   wherein said second circuit means comprises a logic circuit for resetting said transfer counter and for adjusting said random access memory address counter in accordance with the count of said loop position counter outputted in response to a POSITION command from said address decoder and a READ command from said data processing means. .Iaddend..Iadd. 8. The apparatus according to claim 7, wherein third circuit means comprises:   a clock coupled to said mass memory for producing an output pulse at periodic intervals;   a logic gate coupled to said data processing apparatus and to said address decoder for producing an output signal in accordance with a predetermined combination of commands from said address decoder and said data processing apparatus; and a one shot multi-vibrator having an enable input coupled to said logic circuit and a trigger input coupled to said clock for supplying an output signal to said data processing apparatus to cause said data processing apparatus to generate subsequent READ and WRITE commands. .Iaddend..Iadd. 9. The apparatus according to claim 8, and also comprising a two to one multiplexer having a first and second signal input, a control input and an output, the output of said multiplexer coupled to the clock input of said mass memory, said first input of said multiplexer coupled to the output of said clock, said trigger input of said one shot multi-vibrator being coupled to the second signal input of said multiplexer and the output of said one shot multi-vibrator being coupled to the control input of said multiplexer. .Iaddend.