Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure

Abstract

New non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structures are described. With the graded or stepped insulator, electrons or holes can be injected from the gate electrode at low to moderate applied fields. The carriers flow under the applied field into a wide energy band gap insulator having a prescribed charge trapping layer. This layer captures and stores electrons (write operation) or holes (erase operation) with 100% efficiency.

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 
     
       1. A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simuitaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a charge trapping layer embedded in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency. 
     
     
       2. The device of claim 1 comprising a silicon substrate having thereon a relatively thick insulator having embedded therein a layer of impurity atoms proximate to said insulator's second interface at said substrate and said thick insulator having a decreasing band gap in the vicinity of its first interface, said decreasing band gap being produced by ion implantation. 
     
     
       3. The device of claim 1 comprising a silicon substrate having a first relatively thick oxide insulator thereon said insulator having embedded therein a layer of impurity atoms proximate to its interface with said substrate and over which is deposited a relatively thin layer of Si 3  N 4  and a metal or semiconductor contact on the deposited Si 3  N 4  layer. 
     
     
       4. The device of claim 1 comprising a silicon substrate having a first relatively thick oxide insulator thereon said insulator having embedded therein a layer of impurity atoms proximate to said its interface with said substrate, and over which is deposited a plurality of relatively thin pyrolytic or plasma oxide layers, each successively deposited pyrolytic or plasma oxide layer containing an increasing excess silicon content, and a metal or semiconductor contact on the last pyrolytic or plasma deposited oxide layer. 
     
     
       5. A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator adjacent to a relatively thick silicon dioxide insulator layer having embedded therein a layer of impurity atoms. 
     
     
       6. A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure of claim 5 wherein the gate structure comprises a relatively thick oxide on a silicon substrate and a relatively thin layer of Si 3  N 4  formed over the oxide. 
     
     
       7. An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap, said improvement being a layer of impurity atoms embedded in an oxide layer adjacent to the silicon substrate. 
     
     
       8. An improved GIMOS FET structure as in claim 7 wherein the structure comprises a relatively thick oxide on a silicon substrate, having embedded in said oxide a layer of impurity atoms and a plurality of relatively thin pyrolytic or plasma deposited oxide layers formed over the oxide, each successive pyrolytic or plasma deposited oxide layer containing an increasing excess silicon content. 
     
     
       9. In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, and wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact while simultaneously, electron or hole injection from the substrate interface is blocked due to the large insulator band gap at this interface, the improvement being a layer of impurity atoms embedded in said gate oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency. 
     
     
       10. The MOS FET device of claim 9 wherein the insulator comprises an oxide having a thin layer of Si 3  N 4  deposited thereon to provide a low band gap insulator in the vicinity of the gate electrical contact interface. 
     
     
       11. The MOS FET device of claim 9 wherein the insulator comprises an oxide having a decreasing band gap in the vicinity of the gate electrical contact interface, said decreasing band gap being produced by ion implantation. 
     
     
       12. The MOSFET device of claim 9 wherein the insulator comprises a first relatively thick oxide layer over which is deposited a plurality of relatively thin pyrolytic or plasma oxide layers, each successively deposited pyrolytic or plasma oxide layers containing an increasing silicon content. 
     
     
       13. A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a floating polycrystalline silicon charge storage layer in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency. 
     
     
       14. The metal-insulator-metal or metal-insulator-semiconductor structure of claim 13 wherein said injection regions is separate and apart from said gate region. 
     
     
       15. A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator, adjacent to a relatively thick silicon dioxide insulator layer having a floating polycrystalline silicon charge storage layer therein. 
     
     
       16. A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure of claim 15 wherein said injection regions are separate from said gate region. 
     
     
       17. An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap insulator, said improvement being a floating polycrystalline silicon charge storage layer in an oxide layer adjacent to the silicon substrate. .Iadd. 18. A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the insulator has disposed thereon at its first interface, at least one relatively thin successive oxide layer, each successive oxide layer containing an increasing silicon content which provides an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this first interface, while, simultaneously electron or hole injection from said insulator's second interface is blocked, the improvement being a charge trapping layer embedded in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency. .Iaddend..Iadd. 19. A metal-insulator-metal or metal-insulator-semiconductor structure according to claim 18 wherein said charge trapping layer is replaced by a floating polycrystalline silicon charge storage layer. .Iaddend. .Iadd. 20. In a MOSFET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions and wherein said insulator comprises a relatively thick oxide layer over which is deposited at least one relatively thin successive oxide layer, each successively deposited oxide layer containing an increasing silicon content to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact which simultaneously, electron or hole injection from the substrate interface is blocked, the improvement being a layer of impurity atoms embedded in said oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency. .Iaddend..Iadd. 21. A MOSFET device according to claim 20 wherein said layer of impurity atoms is replaced by a floating polycrystalline silicon charge storage layer. .Iaddend.