Engine control

Abstract

An engine control wherein a shaft driven by the engine causes a first signal to be generated and then a second signal after the shaft has rotated through a predetermined degree. The first signal starts a timer into operation, the timer producing a timer pulse of predetermined duration. Time coincidence of the timer signal and second signal indicates that a critical engine speed has been reached and such time coincidence is used to effect a control function. If the shaft rotates in the opposite direction the sequence of generation of the first and second signals in such direction is detected and used to generate a reverse-direction signal which is used to effect a control function. An automatic impedance-changing circuit enables the control to be used with a wide range of batteries.

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS: 
     
       1. Apparatus for controlling the functioning of an engine comprising: .Iadd.A. .Iaddend.a shaft driven by said engine at a speed proportional to the engine speed,   .Iadd.B. .Iaddend.means responsive to rotation of said shaft through a predetermined degree of rotational movement for generating a first signal at the beginning of such movement and a second signal at the end of such movement, p1 .Iadd.C. .Iaddend.timer means for producing a timer signal of predetermined time duration,   .Iadd.D. .Iaddend.means for starting said timer in response to generation of said first signal,   .Iadd.E. .Iaddend.means for effecting a control function in response to time coincidence of said second signal and said timer signal.Iadd., said effecting means including, i. a normally reset flip-flop apparatus,   ii. means for setting said flip-flop apparatus in response to said second signal being generated during the existence of said timer signal, and   iii. means for effecting said control function in response to setting of said flip-flop apparatus.Iaddend.. .[.2. Control apparatus as set forth in claim 1 wherein said means for effecting a control function in response to time coincidence of said second signal and said timer signal comprises:     a normally reset flip-flop means,   means for setting said flip-flop means if said second signal is generated during the existence of said timer signal,   means responsive to the setting of said flip-flop means for effecting said   
     
     
        control function..]. 3. Apparatus as set forth in claim .[.2.]. .Iadd.1 .Iaddend.wherein said timer means includes a capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said 
     
     
        capacitor for charging said capacitor through said variable resistor. 4. Apparatus as set forth in claim .[.2.]. .Iadd.1 .Iaddend.wherein said timer means includes a first capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said first capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said first capacitor for charging said first capacitor through said variable resistor, said apparatus further including: a second capacitor,   means including a manually operable switch for connecting said first and   
     
     
        second capacitors in parallel when said switch is operated. 5. Apparatus as set forth in claim .[.2.]. .Iadd.1 .Iaddend.and further including: a manually operable switch,   means responsive to operation of said switch for resetting said flip-flop   
     
     
        means. 6. Apparatus as set forth in claim .[.2.]. .Iadd.1 .Iaddend.and further including: means including a capacitor for resetting said flip-flop means when the charge on said capacitor drops below a predetermined value, said means further including means for rapidly charging said capacitor to above said value during the existence of said timer signal and means for slowly   
     
     
        discharging said capacitor when said timer signal is not present. 7. Apparatus as set forth in claim .[.2.]. .Iadd.1 .Iaddend.wherein said flip-flop means is resettable by application of a low signal thereto and wherein said flip-flop means cannot be set while a low reset signal is applied thereto, and further including: means including a capacitor for applying a low reset signal to said flip-flop means when the charge on said capacitor is below a predetermined value and a resistor connected across said capacitor for discharge of said capacitor therethrough,   means for charging said capacitor during time coincidence of said timer signal and said second signal and at a greater rate than said capacitor   
     
     
        can discharge through said resistor. 8. Control apparatus comprising: .Iadd.A. .Iaddend.a housing,   .Iadd.B. .Iaddend.a shaft mounted in said housing for rotation about the axis of said shaft,   .Iadd.C. .Iaddend.a magnet mounted on said shaft for movement by said shaft through an orbital path relative to said housing,   .Iadd.D. .Iaddend.magnetically actuated sensor means mounted on said housing adjacent said orbital path for generating a first signal when said magnet has been moved to a fixed point in its orbital path and a second signal when said magnet has been moved a predetermined distance from said fixed point,   .Iadd.E. .Iaddend.timer means for producing a signal of predetermined time duration,   .Iadd.F. .Iaddend.means for starting said timer means into operation in response to generation of said first signal,   .Iadd.G. .Iaddend.means for effecting a control function in response to time coincidence of said second signal and said timer signal .Iadd.wherein said effecting means includes, i. a flip-flop means,   ii. means for setting said flip-flop apparatus in response to said second signal being generated during the existence of said timer signal,   iii. means for effecting said control function in response to the setting     
     
     
        of said flip-flop apparatus.Iaddend.. .[.9.  Control apparatus as set forth in claim 8 wherein said means for effecting a control function in response to time coincidence of said second signal and said timer signal comprises: a flip-flop means,   means for setting said flip-flop means if said second signal is generated during the existence of said timer signal,   means responsive to the setting of said flip-flop means for effecting said   
     
     
        control function..]. 10. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.wherein said timer means includes a capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said 
     
     
        capacitor for charging said capacitor through said variable resistor. 11. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.wherein said timer means includes a first capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said first capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said first capacitor for charging said first capacitor through said variable resistor, said apparatus further including: a second capacitor,   means including a manually operable switch for connecting said first and   
     
     
        second capacitors in parallel when said switch is operated. 12. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.and further including: a manually operable switch,   means responsive to operation of said switch for resetting said flip-flop   
     
     
        means. 13. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.and further including: means including a capacitor for resetting said flip-flop means when the charge on said capacitor drops below a predetermined value, said means further including means for rapidly charging said capacitor to above said value during the existence of said timer signal and means for slowly   
     
     
        discharging said capacitor when said timer signal is not present. 14. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.and further including: means for delaying for a predetermined and substantial period of time following time coincidence of said second signal and said timer signal,   
     
     
        the operation of said means for effecting said control function. 15. Apparatus as set forth in claim .[.9.]. .Iadd.7 .Iaddend.wherein said flip-flop means is resettable by application of a low signal thereto and wherein said flip-flop means cannot be set while a low reset signal is applied thereto, and further including: means including a capacitor for applying a low reset signal to said flip-flop means when the charge on said capacitor is below a predetermined value and a resistor connected across said capacitor for discharge of said capacitor therethrough,   means for charging said capacitor during time coincidence of said timer signal and said second signal and at a greater rate than said capacitor   
     
     
        can discharge through said resistor. 16. Apparatus of the character described, comprising: a housing,   a shaft mounted in said housing for rotation about the axis of said shaft,   a magnet mounted on said shaft for movement thereby through an orbital path relative to said housing,   first and second magnetically actuated sensors mounted on said housing and disposed adjacent said orbital path, said sensors and magnet being dimensioned and said sensors being disposed relative to each other such that as said magnet is moved past said sensors said magnet will first actuate one of said sensors alone, then actuate both sensors   
     
     
        simultaneously, then actuate the other of said sensors alone. 17. Apparatus as set forth in claim .[.16.]. .Iadd.14 .Iaddend.and further including: a flip-flop means,   means responsive to actuation of said first sensor for setting said flip-flop means when said first sensor is actuated,   means responsive to actuation of said second sensor for resetting said flip-flop means when said second sensor is actuated,   means for producing an inhibit signal during actuation of either sensor,   means for producing a reverse-direction signal each time that said flip-flop means is set and said inhibit signal is not present,   means for effecting a control function,   means responsive to the production of a reverse-direction signal for   
     
     
        actuating said control-function-effecting means. 18. Apparatus as set forth in claim .[.17.]. .Iadd.15 .Iaddend.wherein said means responsive to the production of a reverse-direction signal is a latchable means, said apparatus further including: means for resetting said latchable means when said first flip-flop means is reset by actuation of said second sensor and said inhibit signal is not   
     
     
        present. 19. Apparatus as set forth in claim .[.17.]. .Iadd.15 .Iaddend.wherein said means responsive to the production of a reverse-direction signal includes means for counting said reverse-direction signals and for inhibiting operation of said control-function-effecting means until the count of said reverse-direction 
     
     
        signals is greater than one. 20. Apparatus as set forth in claim .[.16.]. .Iadd.14 .Iaddend.and further including: a first flip-flop means,   means responsive to actuation of said first sensor for setting said first flip-flop means when said first sensor is actuated,   means responsive to actuation of said second sensor for resetting said first flip-flop means when said second sensor is actuated,   means for producing an inhibit signal during actuation of either sensor,   means for producing a reverse-directon signal each time that said first flip-flop means is set and said inhibit signal is not present,   a second flip-flop means,   means responsive to the production of a reverse-direction signal for setting said second flip-flop means,   means operable in response to setting of said second flip-flop means for   
     
     
        effecting a control function. 21. Apparatus as set forth in claim .[.20.]. .Iadd.18 .Iaddend.and further including: means for resetting said second flip-flop means when said first flip-flop   
     
     
        means is reset and said inhibit signal is not present. 22. Apparatus as set forth in claim .[.20.]. .Iadd.18 .Iaddend.wherein said means responsive to the production of a reverse-direction signal includes a counting means for counting said reverse-direction signals and for inhibiting setting of said second flip-flop means until the count of said 
     
     
        reverse-direction signals is greater than one. 23. Apparatus as set forth in claim .[.21.]. .Iadd.19 .Iaddend.and further including: means for resetting said second flip-flop means and said counting means when said first flip-flop means is reset and said inhibit signal is not   
     
     
        present. 24. Apparatus as set forth in claim .[.16.]. .Iadd.14 .Iaddend.and further including: timer means for producing a signal of predetermined time duration,   means responsive to each movement of said magnet past said sensors for causing said timer means to produce its signal after said first sensor is deactuated,   a flip-flop means,   means responsive to the presence of said timer signal and actuation of said first sensor for setting said flip-flop means if said first sensor is actuated by said magnet during the existence of said timer signal,   means responsive to the setting of said flip-flop means for effecting a   
     
     
        control function. 25. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.wherein said timer means includes a capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said 
     
     
        capacitor for charging said capacitor through said variable resistor. 26. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.wherein said timer means includes a first capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said first capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said first capacitor for charging said first capacitor through said variable resistor, said apparatus further including: a second capacitor,   means including a manually operable switch for connecting said first and   
     
     
        second capacitor in parallel when said switch is operated. 27. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.and further including: a manually operable switch,   means responsive to operation of said switch for resetting said flip-flop   
     
     
        means. 28. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.and further including: means including a capacitor for resetting said flip-flop means when the charge on said capacitor drops below a predetermined value, said means further including means for rapidly charging said capacitor to above said value during the existence of said timer signal and means for slowly   
     
     
        discharging said capacitor when said timer signal is not present. 29. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.and further including: means for delaying the operation of said control-function-effecting means for a predetermined and substantial period of time following time   
     
     
        coincidence of said second signal and said timer signal. 30. Apparatus as set forth in claim .[.24.]. .Iadd.22 .Iaddend.wherein said flip-flop means is resettable by application of a low signal thereto and wherein said flip-flop means cannot be set while a low reset signal is applied thereto, and further including: means including a capacitor for applying a low reset signal to said flip-flop means when the charge on said capacitor is below a predetermined value and a resistor connected across said capacitor for discharge of said capacitor therethrough,   means for charging said capacitor during time coincidence of said timer signal and first season actuation at a greater rate than said capacitor   
     
     
        can discharge through said resistor. 31. Apparatus as set forth in claim .[.16.]. .Iadd.14 .Iaddend.and further including: a first flip-flop means,   means responsive to actuation of said first sensor for setting said first flip-flop means when said first sensor is actuated,   means responsive to actuation of said second sensor for resetting said first flip-flop means when said second sensor is actuated,   means for producing an inhibit signal during actuation of either sensor,   means for producing a reverse-direction signal each time that said first flip-flop means is set and said inhibit signal is not present,   means responsive to the production of a reverse-direction signal for effecting a control function,   timer means for producing a signal of predetermined time duration,   means for starting said timer means into operation each time said first flip-flop means is reset and said inhibit signal is not present,   a second flip-flop means,   means for setting said second flip-flop means if said first sensor is actuated by said magnet during the existence of said timer signal,   means responsive to the setting of said second flip-flop means for   
     
     
        effecting a control function. 32. Apparatus as set forth in claim .[.31.]. .Iadd.29 .Iaddend.wherein said timer means includes a capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said capacitor for charging said capacitor 
     
     
        through said variable resistor. 33. Apparatus as set forth in claim .[.31.]. .Iadd.29 .Iaddend.wherein said timer means includes a first capacitor for determining the duration of said timer signal in accordance with the length of time that it takes for said first capacitor to charge to a predetermined voltage level and means including a variable resistor connected in series with said first capacitor for charging said first capacitor through said variable resistor, said apparatus further including: a second capacitor,   means including a manually operable switch for connecting said first and   
     
     
        second capacitors in parallel when said switch is operated. 34. An automatic impedance-changing circuit for connecting a load to a direct current voltage source, said circuit having an input connected to one side of said voltage source and an output connected to said load, said load being also connected to the other side of said voltage source for current flow from a voltage source through said circuit and said load, said current comprising: a first current path from the input of said circuit to the output thereof, said first current path having a resistor therein,   a second current path from the input of said circuit to the output thereof, said second current path having a switch means therein for allowing current flow through said second current path when said switch means is closed and for preventing current flow through said second current path when said switch means is open,   means connected between the input of said circuit and said other side of said voltage source for closing said switch means if the voltage at said   
     
     
        input is below a predetermined magnitude. 35. A circuit as set forth in claim .[.34.]. .Iadd.32 .Iaddend.wherein said second current path shorts across said resistor in said first current path when said switch means is 
     
     
        closed. 36. A circuit as set forth in claim .[.34.]. .Iadd.32 .Iaddend.wherein said second current path includes a resistor which is connected in parallel with the first current path resistor when said 
     
     
        switch means is closed. 37. A circuit as set forth in claim .[.36.]. .Iadd.34 .Iaddend.and further including: a third current path from the input of said circuit to the output thereof, said third current path having a switch means therein for allowing current flow through said third current path when said switch means is closed and for preventing current flow through said third current path when said switch means is open,   means connected between the input of said circuit and said other side of said voltage source for closing said third current path switch means if the voltage at said input is below a predetermined magnitude which is less than the predetermined magnitude for closing said second current path   
     
     
        switch means. 38. A circuit as set forth in claim .[.37.]. .Iadd.35 .Iaddend.wherein said third current path shorts across said resistor in said first current path when said third current path switch means is 
     
     
        closed. 39. An automatic impedance-changing circuit for connecting a load to a direct current voltage source, said circuit having an input connected to one side of said voltage source and an output connected to said load, said load also being connected to the other side of said voltage source for current flow from a voltage source through said circuit and said load, said circuit comprising: a first current path from the input of said circuit to the output thereof, said first current path having a resistor therein,   a second current path from the input of said circuit to the output thereof, said second current path having a transistor therein to allow or prevent current flow through said second current path if said transistor is on or off, respectively,   means including a zener diode connected between the input of said circuit and said other side of said battery, said zener diode being conductive if the voltage at said input exceeds the breakdown potential of said zener diode,   means responsive to conduction of said zener diode for turning said transistor off and responsive to non-conduction of said zener diode for   
     
     
        turning said transistor on. 40. A circuit as set forth in claim .[.39.]. .Iadd.37 .Iaddend.wherein said second current path shorts across said 
     
     
        first current path resistor when said transistor is turned on. 41. A circuit as set forth in claim .[.39.]. .Iadd.37 .Iaddend.wherein said second current path includes a resistor in series with said transistor. 
     
     
            A circuit as set forth in claim .[.39.]. .Iadd.37 .Iaddend.and further including: a third current path from the input of said circuit to the output thereof, said third current path having a transistor therein to allow or prevent current flow through said third current path if said transistor is on or off, respectively,   means including a second zener diode connected between the input of said cirucit and said other side of said battery, said second zener diode being conductive if the voltage at said input exceeds the breakdown potential of said second zener diode, said second zener diode having a breakdown potential lower than that of said first-mentioned zener diode,   means responsive to conduction of said second zener diode for turning said third current path transistor off and responsive to non-conduction of said   
     
     
        zener diode for turning said transistor on. 43. A circuit as set forth in claim .[.42.]. .Iadd.40 .Iaddend.wherein said third current path shorts across said first current path resistor when said third current path transistor is turned on.