Digital memory apparatus

Abstract

A low power digital memory comprised of a matrix of memory cells suitable for fabrication by large scale integrated circuit techniques. Each memory cell is comprised of field effect transistors, preferably metal oxide semiconductors. A plurality of cells are fabricated on a single monolithic chip and are interconnected for coincident signal addressing. Power is conserved by periodically pulsing load transistors rather than biasing them continuously on.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows: 
     
       1. A binary memory cell comprising: first and second semiconductors each capable of being either forward biased or off biased;   means interconnecting said first and second semiconductors for holding said first semiconductor off biased in response to said second semiconductor being forward biased and for holding said second semiconductor off biased in response to said first semiconductor being forward biased;   data control means for selectively applying forward and off biasing binary data signals to said first and second semiconductors, said data control means including first and second complementary data signal sources and normally open first and second switches for respectively connecting said first and second semiconductors to said first and second data signal sources, each of said switches comprising a field effect transistor having a gate, a source, and a drain; and   a switch control means coupled to the gates of said first and second switches having at least first and second electrodes and responsive to first and second signals respectively concurrently applied thereto for closing said normally open switches.   
     
     
       2. The memory cell of claim 1 wherein said switch control means comprises a field effect transistor having a gate, a source, and a drain and wherein said first and second electrodes respectively comprise the source and the gate thereof; and means coupling said switch control means drain to said first and second switch gates.   
     
     
       3. A binary memory cell comprising: .[.a.]. first and second semiconductors;   means for selectively forward biasing said first and second semiconductors;   means interconnecting said first and second semiconductors for holding said first semiconductor off biased in response to said second semiconductor being forward biased and for holding said second semiconductor off biased in response to said first semiconductor being forward biased;   first and second capacitive loads respectively coupled to said first and second semiconductors; and   means for periodically .[.discharging.]. .Iadd.restoring the voltage across .Iaddend.said first and second capacitive loads .Iadd.at times independent of the frequency of read or write operations performed on said cells.Iaddend..   
     
     
       4. The memory cell of claim 3 wherein said means for selectively forward biasing said first and second semiconductors includes a source of data signals and first and second normally open switches respectively connecting said source of data signals to said first and second semiconductors. ; and a switch control means having at least first and second electrodes and responsive to first and second signals respectively concurrently applied thereto for closing said normally open switches.   
     
     
       5. A binary memory cell comprising: first and second semiconductors each including a control terminal and first and second current conducting .[.terminls.]. .Iadd.terminals.Iaddend.;   a first source of reference potential;   means connecting each of said first current conducting terminals to said first source of reference potential;   a second source of reference potential;   a first capacitive load means connecting said first semiconductor second current conducting terminal to said second source of reference potential;   a second capacitive load means connecting said second semiconductor second current conducting terminal to said second source of reference potential;   means connecting said first semiconductor second current conducting terminal to said second semiconductor control terminal for holding said second semiconductor cut off when said first semiconductor is conducting;   means connecting said second semiconductor second current conducting terminal to said first semiconductor control terminal for holding said first semiconductor cut off when said second semiconductor is conducting;   data control means for selectively applying forward biasing binary data signals to said first and second semiconductors; and   means for periodically .[.discharging.]. .Iadd.restoring the voltage across .Iaddend.said first and second capacitive loads .Iadd.at times independent of the frequency of read or write operations performed on said cells.Iaddend..   
     
     
       6. The memory cell of claim 5 wherein each of said first and second semiconductors comprises a metal oxide semiconductor and wherein said control and first and second current conducting terminals thereof respectively constitutes the gate, source, and drain of said metal oxide semiconductor. 
     
     
       7. The memory cell of claim 5 wherein said first and second capacitive loads respectively include first and second metal oxide semiconductors each having a gate, a source, and a drain; means respectively connecting said first capacitive load means .[.drain and source.]. .Iadd.source and drain .Iaddend.to said first semiconductor second current conducting terminal and said second source of reference potential;   means respectively connecting said second capacitive load means .[.drain and source.]. .Iadd.source and drain .Iaddend.to said second semiductor second current conducting terminal and said second source of reference potential.   
     
     
       8. The memory cell to claim 5 wherein said data control means includes a source of data signals and first and second switches respectively coupling said data signal source to said first and second semiconductors. 
     
     
       9. The memory cell of claim 8 wherein each of said first and second switches comprises a field effect transistor having a gate, a source, and a drain; a switch control means having at least first and second electrodes and responsive to first and second signals respectively concurrently applied thereto for closing said first and second switches; and means coupling said switch control means to the gates of said first and second switches.   
     
     
       10. A binary memory cell comprising: first and second semiconductors each including a control terminal and first and second current conducting terminals;   a first source of reference potential;   means connecting each of said first current conducting terminals to said first source of reference potential;   a second source of reference potential;   a first capacitive load means connecting said first semiconductor second current conducting terminal to said second source of reference potential;   a second capacitive load means connecting said second semiconductor second current conducting terminal to said second source of reference potential;   means connecting said first semiconductor second current conducting terminal to said second semiconductor control terminal for holding said second semiconductor cut off when said first semiconductor is conducting;   means connecting said second semiconductor second current conducting terminal to said first semiconductor control terminal for holding said first semiconductor cut off when said semiconductor is conducting;   a source of data signals;   first and second switches respectively coupling said data signal source to said first and second semiconductors; and   a switch control means having at least first and second electrodes and responsive to first and second address signals respectively concurrently applied thereto for closing said first and second switches. .[.11. The memory cell of claim 10 wherein said switch control means includes third and fourth semiconductors each having a gate, a source and a drain;   a source of first address signals;   a source of second address signals; and   means respectively coupling said sources of first and second address   
     
     
        signals to said gates of said third and fourth semiconductors..]. 12. A binary memory cell comprising: first and second semiconductors each including a control terminal and first and second current conducting terminals;   a first source of reference potential;   means connecting each of said first current conducting terminals to said first source of reference potential;   a second source of reference potential;   a first capacitive load means connecting said first semiconductor second current conducting terminal to said second source of reference potential;   a second capacitive load means connecting said second semiconductor second current conducting terminal to said second source of reference potential;   means connecting said first semiconductor second current conducting terminal to said second semiconductor control terminal for holding said second semiconductor cut off when said first semiconductor is conducting;   means connecting said second semiconductor second current conducting terminal to said first semiconductor control terminal for holding said first semiconductor cut off when said second semiconductor is conducting;   sense means;   first and second switches respectively coupling said sense means to said first and second semiconductors second current conducting terminals; and   a switch control means having at least first and second electrodes and responsive to first and second address signals respectively concurrently   
     
     
        applied thereto for closing said first and second switches. 13. The memory cell of claim 12 including first and second auxiliary current source means each having a current output terminal; .[.and.]. means respectively connecting said first and second auxiliary current source means output terminals to said .[.first and second semiconductor second current conducting terminals.]. .Iadd.sense means; and   means responsive to the state of said first and second semiconductors for respectively controlling said first and second auxiliary current source means.Iaddend.. .Iadd. 14. In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitance connected through a load to a source of power so as to form a bistable circuit which with one of said semiconductor devices biased conductive and the other of said semiconductor devices biased substantially nonconductive stores a bit of data, the improvement which comprises:   a first semiconductor load device having two terminals connected in series with the source of power and said one semiconductor device and having a third control terminal for regulating the current between the other two terminals of the first semiconductor load device;   a second semiconductor load device having two terminals connected in series with the source of power and said other semiconductor device and having a third control terminal for regulating the current between the other two terminals of the second semiconductor load device; and   pulse means coupled to said control terminals of said first and second semiconductor load devices to normally maintain said current turned off to reduce the power supplied through the load devices to the cross-coupled semiconductor devices below the level necessary to retain a bit of data stored in the bistable circuit while the voltage across said internal capacitance maintains said one cross-coupled semiconductor device biased conductive and said other cross-coupled semiconductor device biased substantially nonconductive and for periodically rendering said current on to restore the voltage across said internal capacitances at intervals sufficiently short to prevent the loss of stored data. .Iaddend..Iadd. 15. The storage cell of claim 14 wherein said cross-coupled semiconductor devices and said first and second load devices are metal oxide semiconductors. .Iaddend..Iadd. 16. The storage cell of claim 14 including:   a first additional semiconductor load device in shunt with the first of said semiconductor load device, said first additional semiconductor load device having a control terminal which can be biased to render the first additional semiconductor load device conductive and nonconductive;   a second additional semiconductor load device in shunt with the second of said semiconductor load device, said second additional semiconductor load device having a control terminal which can be biased to render the second additional semiconductor load device conductive and nonconductive;   differential sense means in series with the first and second additional semiconductor load devices for sensing the state of the storage cell when the first and second additional semiconductor devices are biased conductive whereby the information in the storage cell can be sensed without destroying the information stored in the cell when the first and second load transistors are biased on nonconducting. .Iaddend..Iadd. 17. The storage cell of claim 16 wherein said cross-coupled semiconductor devices and said first and second load devices are metal oxide semiconductors. .Iaddend. .Iadd. 18. In a storage cell having a pair of cross-coupled semiconductor devices with internal capacitance which are connected through a load to a source of power so as to form a bistable circuit which with one of said semiconductor devices biased conductive and the other of said semiconductor devices biased substantially nonconductive stores a bit of data, the improvement comprising:   semiconductor means in said load for controlling the current between the source of power and the pair of semiconductor devices, said semiconductor means having a control terminal which can be biased to turn the current on to supply power through said load to the pair of semiconductor devices or off to reduce the power supplied through said load to the semiconductor devices below the level necessary to retain a bit of data stored in the bistable circuit;   pulse means coupled to said control terminal for normally biasing said current off while charge stored in said internal capacitance maintains said one semiconductor device biased conductive and said other semiconductor device biased substantially nonconductive and for periodically rendering said current on to restore the voltages across said internal capacitances at intervals sufficiently short to preserve the bit of data stored in said cell. .Iaddend..Iadd. 19. A pulse-powered monolithic memory cell comprising:   a bistable circuit means having internal storage charge means;   a power supply connected to said bistable circuit means;   restore means for turning the current from said power supply to an on and to an off or nonsustaining condition with respect to said bistable circuit means, the on condition being of a sufficient level to maintain a data bit stored in said bistable circuit means, and the off or nonsustaining condition being below the necessary level to maintain a data bit stored in said bistable circuit means;   semiconductor switch means connected to said restore means and to said power supply for selecting a controlled high-impedance discharge path for said storage charge means when said power supply current is in an off or non-sustaining condition with respect to said bistable circuit means; and   said power supply current being turned on before the said storage charge means becomes ineffective to return said bistable circuit means to the said same predetermined data bit state as that predetermined data bit state which existed prior to said power supply current being turned to an off or nonsustaining condition. .Iaddend.  .Iadd. 20. A pulse-powered monolithic memory cell as in claim 19 wherein said semiconductor switch means comprises conduction means connected between said power supply output and said bistable circuit and which is in an off state when said power supply current is in an off or nonsustaining condition. .Iaddend. .Iadd. 21. A pulse-powered monolithic memory cell as described in claim 19 further including means connected to said bistable circuit for reading information from and writing information into said bistable circuit..Iaddend. .Iadd. 22. A memory cell as described in claim 21 wherein the frequency with which said power supply current is turned on and off is independent of said reading and writing. .Iaddend. .Iadd. 23. A pulse-powered monolithic memory cell comprising:   a bistable circuit having internal storage charge means;   a power supply means having an output for supplying a current to said bistable circuit;   restore means for switching said current to said bistable circuit between an on and an off or nonsustaining condition;   load means connected between said power supply output and said bistable circuit for providing predetermined operating voltages and power supply currents to said bistable circuit and said storage charge means so that said bistable circuit is maintained in either one of two data bit predetermined states;   semiconductor switch means connected to said restore means and between said power supply and said bistable circuit;   said semiconductor switch means being turned off when said power supply current is in an off or nonsustaining condition so as to select a controlled high impedance discharge path for said storage charge means; and   said power supply current being turned on before the said storage charge means becomes ineffective to return said bistable circuit to the same data bit predetermined state as that predetermined state which existed prior to said power supply current being turned to an off or nonsustaining condition. .Iaddend. .Iadd. 24. A pulse-powered monolithic memory cell as described in claim 23 wherein said high-impedance discharge path for said storage charge means includes a non-linear impedance which is increasing in value when said storage charge means is in a state of change while said power supply current is off. .Iaddend. .Iadd. 25. A pulse-powered monolithic memory cell as described in claim 24 wherein said bistable circuit further includes a pair of cross-coupled transistors. .Iaddend..Iadd. 26. A pulse-powered monolithic memory cell as described in claim 24 wherein said bistable circuit further includes a pair of cross-coupled field-effect transistors. .Iaddend. .Iadd. 27. A pulse-powered monolithic memory cell as described in claim 23 wherein:   said semiconductor switch means is connected in series between said power supply and said bistable circuit; and   said semiconductor switch means is responsive to said means controlling power supply current so as to substantially remove said load means from high impedance discharge path when said power supply current is in an off or nonsustaining condition. .Iaddend. .Iadd. 28. A pulse powered monolithic memory cell as described in claim 23 further including:   differential sense means connected to said bistable circuit means;   said differential sense means being responsive to an energization pulse for reading information from said bistable circuit; and   means connected to said differential sense means for writing information into said bistable circuit. .Iaddend. .Iadd. 29. A memory cell as described in claim 28 wherein the frequency with which said power supply current is turned on and off is independent of said reading and writing..Iaddend.