Pulse code modulated digital audio system

Abstract

The instantaneous amplitude of an analog audio signal is periodically sampled to be converted into multibit binary digital words representing the sampled amplitude. The bits of successive binary words are reproduced serially with appropriate word and frame synchronizing pulses in quaternary coding to pulse code modulate the FM carrier signal used in standard video recording. The recorded signal is demodulated on playback to reproduce successive digital words that are converted into discrete analog values which are low pass filtered to reproduce the original audio signal. The reproduced digital values are also stored in successive address locations of a random access memory. Upon detecting data drop-out, such as by monitoring the FM carrier in the reproduced signal, the memory address sequence is reversed to read out the previously entered values backwards, thus approximating the roughly symmetrical waveform envelope of normal high frequency musical signals so as to avoid discernable discontinuity in the audio output. At the same time, timing pulses are delivered to decrease gradually the bandwidth of the voltage controlled low pass filter to smooth the sample outputs from the memory. When actual data is reacquired, timing pulses used to increment the memory address gradually restore the maximum bandwidth of the voltage controlled low pass filter.

I claim: 
     
       1. A system for minimizing discernable output discontinuities in reproducing digitally transmitted samples of continuous analog signals comprising: means for receiving successive multibit digital words indicative of the instantaneous amplitude value of successive samples of the analog signal;   memory means for entering each successive digital word received to be stored in one of a sequential plurality of word address positions;   dropout detector means for sensing a selected characteristic of the transmitted signal being received to generate an error signal indicative of transmission deficiencies;   memory address means responsive to said error signal for interrupting the normal sequence of entry for said digital words being received and for reading out from said address positions previously entered data words in the reverse sequence of their entry;   digital to analog converter means for receiving either the digital words being entered in forward sequence or digital values derived from the digital words being read out in reverse sequence from the memory means to generate analog values corresponding to successive samples of the continuous analog signal; and,   controlled low pass filter means providing a selectively variable cut-off frequency that decreases gradually from a maximum audio level in response to said error signal and that is gradually restored to or maintained at the maximum level during the absence of said error signal.   
     
     
       2. The system of claim 1 wherein: each digitally transmitted sample is received as a frequency modulated word series of binary bits with synchronizing signals separating each word series;   said receiving means comprises a frequency demodulator for serially detecting the binary value of each bit;   said memory means includes a serial to parallel converter responsive to said synchronizing signals for serially registering each binary bit of an entire word series to be entered in parallel at .[.the.]. .Iadd.a .Iaddend.selected word address position; and,   said dropout detector means comprises a frequency modulation detector for generating said error signal whenever the amplitude of the frequency modulated signal being received is less than a minimum level to prevent the entry of the bits registered in said serial to parallel converter.   
     
     
       3. The system of claim 2 wherein: said synchronizing signals include word synchronizing signals generated during a bit interval following each digital word and frame synchronizing .[.signals.]. .Iadd.signal .Iaddend.generated during one or more discrete word intervals following each predetermined sequence of digital words, said binary bit values being indicated by discrete intermediate modulation levels and said word and frame synchronizing signals being indicated by discrete maximum modulation levels corresponding to the modulation frequency limits of a standard video recorder; and,   said receiving means includes means for detecting the maximum modulation levels of said word and frame synchronizing signals and a phase lock oscillator responsive to the output of said detecting means for generating timing signals for controlling the registering of said bits in said converter and entry of said word series into selected address positions in said memory unit.   
     
     
       4. The system of claim 1 wherein: said .[.control.]. .Iadd.controlled .Iaddend.low pass filter constitutes a voltage controlled low pass filter operating in response to a capacitive charge that is discharged at a fixed rate during each word interval and is incremented towards a maximum charge upon entry of each successive digital word to said memory means whereby the cut-off frequency of said low pass filter is decreased during the presence of said error signal by said discharge and is gradually restored by successive charge increments upon cessation of said error signal.   
     
     
       5. A system for minimizing discernable output discontinuities in reproducing successive multibit digital words indicative of instantaneous samples of a continuous audio signal comprising: memory means having serially addressable word positions for sequentially entering successive multibit digital words to be stored;   means for detecting possible error in the value of each multibit digital word prior to its entry into said memory means;   reversable address means responsive to said detector means for preventing entry of each multibit digital word detected to contain possible error and for reversing the operation of said address means to read out serially from said memory means successive multibit digital words previously entered in the reverse sequence of their entry during detection of said possible error; and,   output means for receiving the successive multibit digital words entered into or read out from said memory means to reproduce an approximation of said continuous audio signals.   
     
     
       6. The system of claim 5 wherein: said output means includes a low pass filter having a selectively controllable cut-off frequency that is gradually reduced from a maximum during detection of possible error and that is thereafter gradually restored to said maximum when successive multibit digital words are again entered into said memory means.   
     
     
       7. The system of claim 6 wherein: said filter means comprises a voltage controlled low pass filter wherein the control voltage is gradually discharged during the intervals between entry of each multibit digital word into said memory means and is incremented by a predetermined amount upon entry of each multibit digital word into said memory means.   
     
     
       8. The system of claim 5 wherein: said successive multibit digital words are manifested as frequency modulated signals; and,   said detecting means comprises a frequency modulator detector for indicating possible error when the amplitude of said frequency modulated signal is below a preselected level.   
     
     
       9. The system of claim 5 wherein: said memory means further includes a serial to parallel converter for serially storing all bits of each multi-digital word prior to entry into one of said word positions.   
     
     
       10. A system for digitally recording and reproducing audio signals comprising: converter means for serially generating a sequence of multibit binary words indicative of the instantaneous amplitude of audio signal samples taken during predetermined sampling intervals;   encoding means for generating .[.the.]. distinctive synchronizing pulses between successive multibit binary words for at least one bit interval and between successive series of multibit binary words for at least one word interval;   modulator means responsive to said multibit binary words and said synchronizing signals for generating a frequency modulated signal within the megaHertz range employed for video recording that which is indicative of the individual bit values and said synchronizing signals; and,   recorder means having a rotary head tape scan system for recording said frequency modulated signals and responsive to the recorded synchronizing signals for reproducing said multibit binary signals upon playback.   
     
     
       11. The system of claim 10 wherein: said modulator means constitutes a frequency modulator of a video recorder employed for modulating a high frequency carrier with monochromatic signals; and   said encoding means generates said synchronizing pluses at respective maximum and minimum amplitudes corresponding to the sync tip and peak white levels of a standard video signal and further includes means for generating said individual bit values at respective intermediate high and low amplitude levels, whereby the video recorder carrier signal is modulated at four distinct modulation frequencies indicative of said synchronizing signals and individual bit values.   
     
     
       12. The system of claim 11 wherein: said recorder means constitutes a helical scan video tape system with a plurality of magnetic recording heads rotated transversely relative to the longitudinal path of a magnetic tape recording medium; and,   said synchronizing .[.pluses.]. .Iadd.pulses .Iaddend.between successive multibit binary words are generated in accordance with the sweep interval of a standard video signal.   
     
     
       13. The system of claim 12 wherein: said recorder means is responsive to the recorded synchronizing signals for switching the signal path during playback between said recording heads during reproduction of said synchronizing pulses between successive word series.   
     
     
       14. The system of claim 11 wherein: said converter means comprises sample and hold circuits for periodically registering the instantaneous amplitude of the analog signal, an analog to digital converter for producing a plurality of binary bit outputs indicative of the instantaneous amplitude registered by said sample and hold circuit, and parallel to serial converter means for sequentially reproducing each of said binary bit outputs in a predetermined order to be applied to said encoding means to generate said intermediate high and low amplitude levels during a predetermined word interval corresponding to the horizontal sweep interval for a standard video signal.   
     
     
       15. A system for digitally recording and reproducing audio signals comprising: means for periodically sampling the instantaneous amplitude of each audio signal at a rate in excess of twice the maximum desired high frequency response;   means for converting each sampled amplitude value to a series of binary bits generated in sequence during a predetermined word interval;   means for generating word synchronizing signals during at least one bit interval between successive digital words and for generating frame synchronizing signals during at least one word interval after each predetermined sequence of binary words;   recorder means adapted to record and reproduce said binary bits and synchronizing signals in the form of frequency modulated monochromatic video signals with each word interval corresponding to the horizontal sweep interval of a standard video signal;   memory means providing serially addressable word positions for sequentially storing successive multibit digital words indicative of said sampled amplitude values;   converter means for demodulating frequency modulated signals reproduced from said recorder means to generate multibit digital words for entry into selected word positions of said memory means;   means responsive to the frequency modulated signal being reproduced for detecting possible error in the value of each multibit digital word prior to its entry into said memory means;   reversable address means responsive to said detector means for preventing entry of each multibit digital word during detection of possible error and for reversing the operation of said address means to read out serially from said memory means successive multibit digital words previously entered in the reverse sequence of their entry; and,   output means for receiving the successive multibit digital words entered into or read out from said memory means to reproduce an approximation of said audio signal.   
     
     
       16. The system of claim 15 wherein: said output means includes a digital to analog converter to generate analog values corresponding to the sample values of the successive multibit digital words, and .[.control.]. .Iadd.controlled .Iaddend.low pass filter means providing a selectively variable cut-off frequency that decreases gradually from a maximum audio level during detection of possible error and is gradually restored to or maintained at the maximum level when no possible error is detected.   
     
     
       17. The system of claim 15 wherein: said sampling means includes multiplexing means for periodically sampling the instantaneous amplitude of each of a plurality of input audio signals during the same portion of each frame interval.   
     
     
       18. The system of claim 17 wherein: said recorder means includes a frequency modulator for modulating a high frequency carrier signal in response to said binary bits and synchronizing signals at discrete modulation levels within the range of approximately 3.8 to 5.4 megaHertz.   
     
     
       19. The system of claim 18 wherein: said modulator produces frequency modulated outputs at approximately 3.8 and 5.4 megaHertz in response to said synchronizing signals and at two discrete intermediate frequencies in response to the binary value of each binary bit.   
     
     
       20. The system of claim 15 wherein: said means for detecting possible error includes a frequency modulation detector responsive to the amplitude of said frequency modulation signal reproduced by said recorder means to generate an error signal whenever the amplitude of said frequency modulation signal is below a predetermined level.   
     
     
       21. The system of claim 15 wherein: said means for generating word synchronizing pulses constitutes a quarternary encoder .Iadd.and .Iaddend.for generating said synchronizing pulses at the sync tip and peak white modulation limit of a standard video signal input to said recorder means for generating intermediate output levels indicative of the binary value of each binary bit.   
     
     
       22. The system of claim 21 wherein: said recorder means constitutes a video tape recorder having a helical scan, rotary magnetic head system and head switching circuit responsive to said frame synchronizing pulses being reproduced for switching the signal path between magnetic heads at the beginning and end of each helical scan only during reproduction of said frame synchronizing signals.   
     
     
       23. A method for digitally recording and reproducing audio signals comprising: taking successive samples of the amplitude of each audio signal at a rate of at least twice the desired high frequency audio response;   converting each sample to a multibit binary word indicative of its amplitude value;   serially generating each bit of said multibit binary words with synchronizing pulses separating adjacent words in the series and frame pulses separating repetitive sequences of said pulses, said frame pulses being generated during one or more word intervals at a rate corresponding to the horizontal sync rate of a standard video signal;   applying said multibit binary words to the video input of a video recorder to modulate the internal high frequency carrier at four discrete levels between the sync tip and peak white modulation limits of a standard video signal,   recording and reproducing the modulated signals with a rotary head, helical scan video tape system;   demodulating the frequency modulated signals to reproduce said multibit binary words in sequence;   sequentially storing said multibit binary words being reproduced in a predetermined sequence of memory address positions;   monitoring the frequency modulation of the signal being reproduced to detect possible error;   interrupting the entry of the multibit binary words being reproduced into said memory address positions and reversing the address sequence to read out the multibit binary words previously stored in a reverse sequence during detection of possible error;   converting said multibit binary words being entered into or read out from said address position into an analog value representative of said sampled amplitude value; and   low pass filtering said analog values to reproduce an approximation of said analog signals.   
     
     
       24. The method of claim 23 wherein: said low pass filtering provides a selectively variable cutoff frequency normally maintained at a maximum corresponding to the desired high requency audio response, said cutoff frequency being gradually reduced during detection of possible error and gradually restored to said maximum after detection of possible error has ceased.   
     
     
       25. The method of claim 23 wherein: said high frequency carrier is modulated by said frame and sync pulses at the sync tip and peak white modulation limits of a standard video signal input, while said binary bits are modulated at two discrete intermediate levels between these modulation limits.   
     
     
       26. The method of claim 23 wherein: said samples are taken in succession from each of four audio input channels with successive samples from each channel being taken at equal intervals in accordance with a predetermined multiplexing sequence. .Iadd. 27. A system for digitally recording and reproducing audio signals comprising:   means for sequentially sampling the instaneous amplitude of the audio signals periodically at fixed intervals at a rate in excess of twice the maximum desired high frequency response;   analog-to-digital converter means for generating a series of multibit digital words indicative of corresponding sampled amplitude values;   coding means for generating recording signals indicative of the multibit digital words generated by said converter means together with periodic synchronizing signals to identify successive multibit digital words;   video recorder means for recording and reproducing said recording signals indicative of said multibit digital words and said synchronizing pulses for use in generating a substantial duplication of the original audio signal;   memory means for storing a selected plurality of the multibit digital words being reproduced in a predetermined order;   dropout detector means responsive to the recording signal being reproduced for generating a signal indicative of possible data errors in the digital words being reproduced; and,   compensation means responsive to each indication of possible error by said dropout detector means for generating a substitute digital word sequence in accordance with the multibit digital words previously stored in said memory means to be supplied in place of the digital words being reproduced with possible errors in generating said duplication of the original audio   
     
     
        signal. .Iaddend. .Iadd. 28.  the system of claim 27 further comprising: a decoding means responsive to the periodic synchronizing signals reproduced from said video ecorder means for reproducing the multibit sequence in each digital word;   serial-to-parallel converter means for storing each successive multibit digital word reproduced by said decoding means to be read out at intervals corresponding to the original audio signal sampling sequence; and,   digital-to-analog converter means for receiving each multibit digital word to produce an accurate simulation of said original audio signal. .Iaddend.   
     
     
        .Iadd. 29.  The system of claim 28 wherein: said sampling means includes means for sampling the instantaneous amplitude of audio signals in each of a plurality of audio channels at fixed intervals; and,   the decoding means includes timing means for generating the recording signals indicative of the multibit digital words for each different audio channel in a predetermined sequence together with other multibit digital words. .Iaddend..Iadd. 30. The system of claim 29 further comprising:   serial-to-parallel converter means for storing successive multibit digital words reproduced by said decoding means to be read out at fixed intervals corresponding to the original audio sampling intervals for each audio channel;   a plurality of digital-to-analog converter means each receiving successive multibit digital words to generate a corresponding audio signal for respective ones of said audio channels; and,   control means responsive to said periodic synchronizing signals for reading out the multibit digital words indicative of the sampled amplitude values for each audio channel to a respective one of said digital-to-analog converter means at fixed intervals corresponding to the original sequence of periodic sampling intervals for the respective audio channels to accurately reproduce the original audio signal in each channel. .Iaddend.   
     
     
        .Iadd. 31.  The system of claim 30 wherein: said memory means has a capacity for storing a selected plurality of multibit digital words being reproduced in a predetermined order for each audio channel; and,   said compensation means is responsive to each indication of possible error by said dropout detector means for generating a substitute digital word sequence for each audio channel, in accordance with the multibit digital words previously stored in said memory means for each channel to be supplied to the respective ones of said plurality of digital-to-analog converter means in place of digital words being reproduced with possible errors, thereby simulating the sampled audio signal for each channel. .Iaddend. .Iadd. 32. The system of claim 27 wherein:   the periodic synchronizing signals generated by said coding means comprise first synchronizing signals generated at fixed intervals, which correspond to the horizontal synchronizing signal intervals of a standard video television signal, to separate successive groupings of said multibit digital words. .Iaddend..Iadd. 33. The system of claim 32 wherein:   said periodic synchronizing signals further include second synchronizing signals generated at periodic intervals between said first synchronizing signals to separate successive multibit digital words. .Iaddend..Iadd. 34. The system of claim 27 wherein:   said coding means includes means for generating periodic synchronizing pulses and frequency modulation means responsive to the individual bit values of said multibit binary words and to said synchronizing pulses whereby said recording signal is frequency modulated within the megaHertz range employed in standard video recording; and,   said dropout detector means comprises a frequency modulation detector for generating a signal indicative of possible data errors in the digital words being reproduced whenever the amplitude of the frequency modulated signal being reproduced is less than a predetermined minimum level.