Double master mask process for integrated circuit manufacture

Abstract

A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide/nitride layer is stripped away and a second oxide/nitride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide/nitride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other. The diffusion cycle used to form the collector contact and emitter regions simultaneously anneals the ion implanted resistor region to form a high value resistor of closely controlled tolerances. In conjunction with the use of the first master mask, a base region and isolation region which are self-aligned with respect to each other are formed through the use of a "base washout" process which maintains self-alignment without the use of additional process steps.

What is claimed is:  .[.1. A self-aligned method of manufacturing integrated circuits comprising the steps of: 
     
        second masking means..]. 2. The self-aligned method of manufacturing integrated circuits as recited in claim .[.1.]. .Iadd.17 .Iaddend.further comprising the step: .[.a).]. forming an additional set of .[.semiconductor device.]. .Iadd.doped .Iaddend.regions by applying impurities through portions of said .[.first.]. .Iadd.third .Iaddend.masking means not constituted by said .Iadd.second .Iaddend.predetermined pattern of openings.  .[.3. The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said first masking means comprises at least two layers which are selectively etchable with respect to each other..]. .[.4. The self-aligned method of manufacturing integrated circuits as recited in claim 3 wherein at least one of said layers is silicon dioxide..]. .[.5. The self-aligned method of manufacturing integrated circuits as recited in claim 3 wherein at least one of said selectively etchable layers is silicon nitride..].   
     
     
           The self-aligned method of manufacturing integrated circuits as recited in claim .[.2.]. .Iadd.17 .Iaddend.wherein said .[.second.]. .Iadd.third .Iaddend.masking means comprises at least two layers which are selectively etchable with respect to each other.  .[.7. The self-aligned method of manufacturing integrated circuits as recited in claim 6 wherein at least one of said layers is silicon dioxide..]. .[.8. The self-aligned method of manufacturing integrated circuits as recited in claim 6 wherein at least one of said selectively etchable layers is silicon nitride..]. .[.9. The self-aligned method of manufacturing integrated circuits as recited in claim 2 wherein said upper layer is an epitaxially deposited silicon 
     
     
        layer..]. 10. The self-aligned method of manufacturing integrated circuits as recited in claim 2 wherein said semiconductor substrate is silicon. 
     
     
            The self-aligned method of manufacturing integrated circuits recited in claim .[.1.]. .Iadd.17 .Iaddend.wherein said first set of .[.device.]. .Iadd.doped .Iaddend.regions comprise the base region and the isolation 
     
     
        region of a semiconductor device. 12. The self-aligned method of manufacturing integrated circuits recited in claim 11 wherein said first set of .[.semiconductor device.]. .Iadd.doped .Iaddend.regions 
     
     
        .Iadd.further .Iaddend.comprise resistor contact regions. 13. The self-aligned method of manufacturing integrated circuits recited in claim .[.1.]. .Iadd.17 .Iaddend.wherein said second .[.set of semiconductor device.]. .Iadd.predetermined pattern of .Iaddend.openings comprise the collector contact, base contact and emitter regions of a semiconductor 
     
     
        device. 14. The self-aligned method of manufacturing integrated circuits recited in claim 2 wherein said step of applying impurities through portions of said .[.first.]. .Iadd.third .Iaddend.masking means not constituted by said .Iadd.second .Iaddend.predetermined pattern of 
     
     
        openings comprises ion implantation. 15. A self-aligned method of manufacturing integrated circuits comprising the steps of: (a) providing a buried layer and an upper layer over a semiconductor substrate, said upper layer and said buried layer being of a first conductivity type, and said substrate being of a second conductivity type opposite to said first conductivity type;   (b) .[.depositing.]. .Iadd.forming .Iaddend.a first masking layer over .[.the upper surface of.]. said upper layer;   (c) .[.depositing.]. .Iadd.forming .Iaddend.a second masking layer .[.of the upper surface of.]. .Iadd.over .Iaddend.said first masking layer;   (d) forming a predetermined pattern of openings in said second layer, said predetermined pattern comprising a first and a second group of openings;   (e) forming a first group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said first group of openings as an etching mask;   (f) forming a second group of semiconductor device regions by applying impurities through openings etched through said first masking layer using said second group of openings as an etching mask; .[.g) forming shallow device regions, said shallow device regions overlaying the upper surfaces of said first and said second group of device regions and said shallow device regions being formed irrespective of said predetermined pattern of openings;.].   .[.h).]. .Iadd.(g) .Iaddend.removing said first and said second masking layers;   .[.i) depositing.]. .Iadd.(h) forming .Iaddend.a third masking layer over .[.the upper surface of.]. said upper layer;   .[.j) depositing.]. .Iadd.(i) forming .Iaddend.a fourth masking layer over .[.the upper surface of.]. said third masking layer;   .[.k).]. .Iadd.(j) .Iaddend.forming a .Iadd.second .Iaddend.predetermined pattern of openings in said fourth layer, said .Iadd.second .Iaddend.predetermined pattern comprising a third and a fourth group of openings;   .[.1).]. .Iadd.(k) .Iaddend.forming a third group of semiconductor device regions by applying impurities through openings etched through said third masking layer using said third group of openings as an etching mask; and   .[.m).]. .Iadd.(l) .Iaddend.forming a group of contact openings through said third masking layer using said fourth group of openings as an etching   
     
     
        mask. 16. A self-aligned method of manufacturing integrated circuits as recited in claim 15 wherein said step of forming a second group of semiconductor device regions includes the reopening of said first group of openings simultaneous with the etching of openings using said second group of openings as an etching mask. .Iadd. 17. A self-aligned method for manufacturing integrated circuits comprising the steps of: providing a semiconductor substrate having a buried layer therein, and an epitaxial layer overlying said substrate and having a surface, said buried layer and said epitaxial layer being of a first conductivity type and said substrate being of a second conductivity type opposite said first conductivity type; forming a first masking means over said surface; forming a second masking means over said first masking means, said second masking means exhibiting a slow etch rate in an etchant for said first masking means; forming a predetermined pattern of openings in said second masking means; etching openings in said first masking means through some but not all of said openings in said second masking means; forming a first set of doped regions by selectively applying impurities of a second conductivity type opposite said first conductivity type through said openings in said first masking means; etching said first masking means through all of said openings in said second masking means; forming a second set of doped regions by applying impurities of said second conductivity type through all of said openings; removing said first and said second masking means from said surface; forming a third masking means over said surface and said doped regions, said third masking means having a second predetermined pattern of openings formed therein; forming a third set of doped regions by selectively applying impurities of said first conductivity type through some but not all of said openings of said second predetermined pattern of openings; and applying contact means to said doped regions through said second predetermined pattern of openings. .Iaddend. .Iadd. 18. The self-aligned method of claim 15 wherein said step of forming said group of contact openings contacts said first, second and third group of semiconductor device regions. .Iaddend..Iadd. 19. The self-aligned method of claim 15 wherein said first and second groups of semiconductor device regions are of the same conductivity type. .Iaddend..Iadd. 20. The self-aligned method of claim 19 wherein said third group of semiconductor device regions is of the opposite conductivity type. .Iaddend..Iadd. 21. The self-aligned method of claim 15 wherein said step of forming a second group of semiconductor device regions includes the reopening of said first group of openings simultaneous with the etching of openings using said second group of openings as an etching mask. .Iaddend. .Iadd. 22. The self-aligned method of manufacturing integrated circuits as recited in claim 17 wherein said first masking means is silicon dioxide. .Iaddend..Iadd. 23. The self-aligned method of manufacturing integrated circuits as recited in claim 17 wherein said second masking means is silicon nitride. .Iaddend..Iadd. 24. The self-aligned method of manufacturing integrated circuits as recited in claim 6 wherein said third masking means comprises sequential layers of silicon dioxide and silicon nitride. .Iaddend.