Semiconductor device comprising an insulated gate field effect transistor and method of manufacturing the same

Abstract

Method of making an insulated gate field effect transistor is described in which the surface of a silicon semiconductor is covered in whole or in part with a layer of a masking material which masks against oxidation, such as silicon nitride. Areas of the silicon surface are exposed for the source and drain regions, leaving the oxidation mask over the future channel. When the source and drain regions have been made, as for example by diffusion, the device is subjected to oxidation, causing the growth of a thick oxide which sinks into the silicon surface where it is not masked by the oxidation mask. Among the advantages obtained are fewer precise masking steps, a flatter device surface, and reduced gate overlap of the source and drain.

What is claimed is: .[.1. A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion an impurity masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of masking material other than silicon oxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of the opposite type conductivity in said body portion, subjecting at least surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by oxidation masking material forming a silicon mesa under said oxidation masking material applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions..]. .[.2. A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion an impurity masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of masking material other than silicon oxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to a oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated by an insulating layer which is substantially thinner than the said penetrated grown oxide from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions..]. .[.3. A method as set forth in claim 2 wherein the oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface regions..]. .[.4. A method as set forth in claim 2 wherein the gate electrode is provided on the oxidation masking material..]. .[.5. A method as set forth in claim 2 wherein silicon nitride is the oxidation 
     
        masking material..]. .[.6.  A method as set forth in claim 2 wherein, after the oxidation treatment, the portion of the masking layer between the opposite type surface regions is removed and replaced by an insulating layer which is thinner than the penetrated grown oxide, and the gate electrode is provided on the insulating layer..]. .[.7. A method as set forth in claim 2 wherein the body portion is provided with a masking layer which between the apertures consist essentially of a silicon oxide layer on the silicon body portion with said oxidation masking material on the silicon oxide, and following the oxidation treatment the oxidation masking material is removed and the gate electrode provided in its place on the 
     
     
        silicon oxide layer..]. 8. A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel a layer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, subjecting the non-masked surface portions of the body portion to a first oxidation treatment causing the growth of a silicon oxide that penetrates into the body portion except where masked by the oxidation masking material, providing adjacent opposite sides of the masking layer spaced apertures in said oxide layer, diffusing impurities into the body portion through said apertures to form opposite type source and drain regions and subjecting the body to a second oxidation treatment to cause the growth of an oxide in the apertures that penetrates into the body portion, applying a gate electrode insulated from and over the surface portion to constitute the transistor channel, and applying source and drain connections to the opposite type surface 
     
     
        regions. 9. A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel and the source and drain regions a lyer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, subjecting the nonmasked surface portions of the body portion to a first oxidation treatment causing the growth of a silicon oxide that penetrates into the body except where masked by the oxidation masking material, removing spaced parts of said masking layer over the source and drain regions to be made, diffusing impurities into the body portions exposed by the removed masking layer parts to form opposite type source and drain regions and subjecting exposed body portions adjacent the surface portion to constitute the transistor channel to a second oxidation treatment to cause the growth of an oxide thereat that penetrates into the body portions, applying a gate electrode insulated from and over the surface portion to constitute the transistor channel, and applying source and drain 
     
     
        connections to the opposite type surface regions. 10. A method as set forth in claim 9 wherein the second oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface 
     
     
        regions. 11. A method as set forth in claim 9 wherein the gate electrode 
     
     
        is provided on the oxidation masking material. 12. A method as set forth 
     
     
        in claim 9 wherein silicon nitride is the oxidation masking material. 13. A method as set forth in claim 9 wherein, after the second oxidation treatment, the portion of the masking layer between the opposite type surface region is removed and replaced by an insulating layer which is thinner than the grown oxide, and the gate electrode is provided on the 
     
     
        insulating layer. 14. A method as set forth in claim 9 wherein the body portion is provided with a masking layer which between the apertures consists essentially of a silicon oxide layer on the silicon body portion with said oxidation masking material on the oxide layer, and following the second oxidation treatment the masking material is removed and the gate 
     
     
        electrode provided in its place on the silicon oxide layer. 15. A method as set forth in claim 9 wherein the various oxide layers with various thicknesses are grown to penetrate over various distances into the body portion so as to provide a substantially flat surface on top, the gate electrode and source and drain connections having portions extending over the said substantially flat surface. .[.16. A method of manufacturing an insulating gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of the body portion a layer of diffusion masking material which at least over part of its thickness is of a material other than silicon oxide and also capable of masking the underlying silicon against oxidation, providing spaced apertures in said masking layer, diffusing impurities into the body portion through said apertures to form opposite type source and drain regions, removing the masking layer except for a portion overlying the body surface between the source and drain regions, subjecting the body portion to an oxidation treatment to cause the growth of an oxide on the non-masked surface that penetrates into the body portion, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying 
     
     
        source and drain connections to the opposite type surface regions..]. 17. A method of manufacturing an insulated gate field-effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing only on a surface portion of said body portion to constitute the transistor channel and the source and drain regions a layer of masking material which over at least part of its thickness is of a material other than silicon oxide and capable of masking the underlying silicon against oxidation, subjecting the nonmasked surface portions of the body portion to an oxidation treatment causing the growth of a silicon oxide that penetrates into the body portion except where masked by the masking material, providing spaced opposite type source and drain regions in the semiconductive part not covered by said silicon oxide, applying a gate electrode insulated from and over the surface portion extending between the opposite type source and drain regions, and applying source 
     
     
        and drain connections to the opposite type source and drain regions. 18. A method as set forth in claim 17 wherein the masking layer over at least part of its thickness comprises silicon nitride. .[.19. A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion a diffusion masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of silicon nitride and also capable of masking the underlying silicon against oxidation, providing by diffusion through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least the surface portion of the body portion overlying the opposite type surface regions to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by said oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections through holes in the said penetrated grown oxide to the opposite type surface regions..]. .[.20. A method as set forth in claim 19 wherein the oxidation treatment is continued until the thickness of the grown silicon oxide is substantially greater than that of the portion of the masking layer between the opposite type surface regions..]. .Iadd. 21. A method as set forth in claim 18 wherein the silicon nitride is removed before the gate electrode is applied. .Iaddend..Iadd. 22. A method as set forth in claim 21 wherein the masking layer comprises an intermediate silicon oxide layer on the silicon body portion and a silicon nitride layer on the oxide layer and wherein before applying the gate electrode the silicon nitride layer is removed whereafter the gate electrode is applied over part of the intermediate oxide layer. .Iaddend..Iadd. 23. A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion an impurity masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures and at least over part of its thickness being of masking material other than silicon oxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by oxidation masking material forming a silicon mesa under said oxidation masking material, after the oxidation treatment removing the portion of the masking layer between the opposite type surface regions and replacing said portion of the masking layer by an insulating layer which is thinner than the penetrated grown oxide, providing a gate electrode on the thinner insulating layer, and applying source and drain connections to the opposite type surface regions. .Iaddend. .Iadd. 24. A method of manufacturing an insulated gate field effect transistor comprising providing a silicon semiconductive body portion of one-type conductivity, providing on a surface of said body portion an impurity masking layer having at least two adjacent apertures with at least the portion of said masking layer between said apertures consisting essentially of a silicon oxide layer on the silicon body and on the silicon oxide a layer of masking material other than silicon oxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of the opposite type conductivity in said body portion, thereafter subjecting at least surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon oxide that penetrates into the body portion except where masked by oxidation masking material forming a silicon mesa under said oxidation masking material, following the oxidation treatment removing the oxidation masking material and providing a gate electrode in its place on the silicon oxide layer, said silicon oxide layer under the gate electrode being substantially thinner than the said penetrated grown oxide, and applying source and drain connections to the opposite type surface regions. .Iaddend.