Plural channel error correcting apparatus and methods

Abstract

Error correcting apparatus is provided for correcting plural channels in error in a parallel channel information system. The information is encoded in a cross-channel direction as well as along the channel length. The encoded message after storage or transmission is decoded in the cross-channel direction and error correction provided in the in-channel direction in a given number of indicated channels. Orthogonally symmetrical redundancy enhances error correction while tending to minimize hardware. Plural independent codes interact to correct the plural channels in error. The error correcting capabilities of the codes may be matched, no limitation thereto intended.

What is claimed is: 
     
       1. An error correcting system for correcting up to two channels in error in a multiparallel channel data handling system comprising: an encoding system including cyclic check bit generating means for generating an orthogonally symmetrical check bit for each of said parallel channels, said check bits being entered into said respective channels and being grouped to form a cross-channel check byte;   said encoding system further including parity bit generating means for generating parity bits for information bytes formed in a cross-channel direction, means for entering said parity bits into one of said parallel channels;   means for decoding said data by means of said parity bits and information bytes formed in the cross-channel direction to detect errors; and   means for correcting errors in all the bytes extending along any one or more channels including cyclic means generating a cyclic syndrome vector simultaneously to a parity syndrome vector based on the errors detected in the decoding utilizing only said cross-track bytes.   
     
     
       2. An error correcting system according to claim 1, wherein said parity bit generating means generates another parity bit for each of said groups of check bits forming a cross-channel byte so that said means for decoding is applicable to said cross-track check byte and said means for correcting errors includes the said check bits in any one or two designated channels of said parallel channels. 
     
     
       3. An error correcting system according to claim 1, wherein said means for generating check bits including means for computing said cross-track check bytes according to the relationship:   C=TB.sub.1 ⊕T.sup.2 B.sub.2 ⊕T.sup.3 B.sub.3 ⊕ . . . ⊕T.sup.n.sbsp.2 B.sub.n.sbsb.2     where T is the companion matrix of an irreducible binary polynominal g(x) of degree n 2  and T i  represents the i th  power of the matrix T and B i  represents the n 2  data bytes of n 1  -1 bits.   
     
     
       4. An error correcting system according to claim 3, wherein said means for generating check bits includes a shift register which premultiplies the incoming bytes by T. 
     
     
       5. An error correcting system according to claim 3, including means in said decoder for computing two syndrome bytes S 1  and S 2  each of n 1  -1 bits according to the relationship:   S.sub.1 =P⊕P     which is derived from modulo 2 addition of the generated parity byte P and the received parity byte P; and     S.sub.2 =C⊕T.sup.1 B.sub.1 ⊕T.sup.2 B.sub.2 ⊕ . . . ⊕T.sup.n.sbsp.2 B.sub.n.sbsb.2     wherein an underlined symbol indicates a byte of said received message corresponding to nonunderlined symbols in said sent message.   
     
     
       6. An error correcting system according to claim 5, wherein said means for computing two syndrome bytes S 1  and S 2  includes feedback shift registers, said shift register for computing S 2  being a backward shifting register having a premultiplier T n .sbsp.2. 
     
     
       7. An error correcting system according to claim 1, means supplying error location pointers, said means for decoding includes an N indicator means for providing the control signal N 1 , N 3 , and Q in response to error pointers indicating the channel in error, the N 1  signal indicates that only one channel pointer or none are on, the N 3  signal indicates that more than two channel pointers are on, and the Q output represents the pointers Q 0  -Q 8 , and means for inhibiting said control signals Q when N 1  or N 3  is on. 
     
     
       8. An error correcting system according to claim 7, wherein said means for decoding further includes means for generating the error track parameters I, i, and j-i from the pointer control signals Q, the error channel parameter I being a new pointer which identifies the first erroneous data channel called the I th  channel, the signals i being generated as binary numbers from the I pointer signals and the j-i signals indicating the responsive distance of the channels in error. 
     
     
       9. An error correcting system according to claim 8, wherein said means for decoding includes means for generating the error pattern e 2  from the S 1  and T -i  S 2  inputs controlled by said j-i inputs according to the relationships:   e.sub.2 =M.sub.j-i [S.sub.1 ⊕T.sup.-1 S.sub.2 ]     where:     M.sub.j-i =[I.sub.d ⊕T.sup.j-i ].sup.-1     if j-1≠0 and j≠8     M.sub.j-i =I.sub.d     if j-i=0 or j=8   and I d  is an identity matrix.   
     
     
       10. An error correcting system according to claim 9, wherein said means for decoding includes means for generating a code pointer Q' and means for generating a count R, said means for generating a code pointer having the count R, the control signal N 1 , and e 2  as inputs; said code pointer generator generating the code pointer Q' indicative of a single track in error when said input signal e 2  =0 and N 1  is on, the R count from said ring counter indicating the channel in error. 
     
     
       11. An error correcting system according to claim 1, wherein said means for correcting errors in all the bytes extending along any one channel or any two designated channels includes modulo 2 adder circuits for comparing the error patterns S 1  and e 2  with said channel bytes of information Z 0 , Z 1 , Z 2 , . . . Z 7  and producing corrected information in accordance with said error patterns to obtain the corrected information Z 0 , Z 1 , . . . Z 7 . 
     
     
       12. The method of transferring successive N-bit signal bytes through N channels, one signal from each byte in a channel, including the steps of: A. at a transmitter, 1. collecting N-1 data signal bytes;   2. generating a check bit signal byte for said N-1 data signal bytes in an orthogonally symmetrical manner;   3. transferring said N-1 data and check bit signal bytes as a signal set over said N channels;   repeating (1), (2), and (3) until signals have been transferred; and     B. at a receiver for said transferred data signal bytes in each said set, 4. computing a second check bit signal byte supposedly identical to said transferred check bit signal byte;   5. comparing the check bit signal byte and from said comparison generating an error pattern for signals along a given channel;   6. indicating which channel is said given channel having signals in error; and   7. applying said error pattern to correct signals in said given channel for such signal set.     
     
     
       13. The method set forth in claim 12 further including the steps of: A-1. at the transmitter, 8. generating an independent check bit signal for each of said bytes including said check bit signal byte as they are being transferred;   B-1. at the receiver,   9. combining said independent check bits for all of said bytes in a given signal set with said check bit signal byte for generating first and second error pattern signals respectively for first and second chanels;   10. repeating step (6) for each signal set for indicating which two channels have signals in error; and   11. selectively modifying step (7) to correct signals in two of said channels rather than correcting errors in but one channel for such signal set.     
     
     
       14. The method set forth in claim 12 further in said step (2) generating said check bit signal byte in accordance with an identity matrix and N-1 companion matrices, each matrix consisting of n column vector operator signals modulo a selected polynomial; and B-2. at said receiver, 12. processing said data bytes in each said channel such that the operational relationships between each and every data bit and each and every check bit with respect to said column vector operators remain the same even though the signals are along the respective channels.     
     
     
       15. The method set forth in claim 14 further including selecting said independent check bit signal to be a parity signal and selecting a magnetic tape unit having nine tracks with a central one of said tracks being the parity track and the other eight tracks, including the outside tracks, being data tracks, and repeatedly performing said steps (1) through (3), (8) for recording a plurality of successive end bit signal bytes on said tape and repeatedly performing steps (4) through (7) and (9) through (12) for reading back the signals recorded on such tape. 
     
     
       16. The method of operating a multichannel digital signal apparatus, including the steps of:   selecting a first group of said channels to sequentially transfer plural sets of data signals, the number of signals in each channel for each set being one less than the number of channels in said first group;   for each said set, generating a first check byte having one signal in each channel for said each set of said first group and arranging all signals in each said set including said check byte signals to have orthogonal symmetry; and   generating second check signals based on said arranging and supplying said second check signals to a channel other than said first group of channels.   
     
     
       17. The method set forth in claim 16 selecting a polynomial from the Galois Field 2 b  for said first check byte, where b is the number of channels in said first group and generating said second check signals in a manner not describable in terms of symbols in said Galois Field 2 b . 
     
     
       18. The method set forth in claim 16 including generating said second check signals as parity signals based upon one signal from each of said channels in said first set and aligned in a cross-channel direction. 
     
     
       19. The method of operating a multichannel digital signal transfer system, including the step:   selecting first and second independent error correction codes, each having a given error correction capability, said first error correction code exhibiting orthogonal symmetry;   dividing the digital signals into sets along the respective channels into a number of signals less than the number of channels;   establishing a first check bit byte in accordance with a given orthogonal symmetry and a polynomial in said first error correction code;   establishing a second check bit byte in accordance with said second error correction code; and   selectively using one or both of said codes to correct errors in a given one of said channels.   
     
     
       20. The method set forth in claim 19 including selectively using both of said codes to correct errors and including shifting data signals in the respective sets in a forward direction for processing signals in a so-called forward direction including premultiplying by a matrix T of said polynomial, then repeatedly matrix multiplying by a matrix T by shifting in a forward direction and including linear feedback in said shifting in accordance with said polynomial; and selectively processing said signals in a backward direction including premultiplying said signals in the respective sets by a matrix T 7  of said polynomial and including matrix multiplying said signals in such sets by T -1  for seven times in a so-called backward direction.   
     
     
       21. The method set forth in claim 19 further including selecting said first independent error correction code to have orthogonal symmetry in accordance with a given polynomial and arranging column vectors based upon said polynomial in a predetermined manner such that said check bit signals mathematically established said check bit byte in a predetermined relationship to the data signals in a cross-channel direction, a first position being an end position of an array including said data signals and said first check bit byte signals. 
     
     
       22. The method set forth in claim 21 further including selecting said column vectors to generate error correction and error bit generating matrices for placing said check bit byte in a central position of said data signals array rather than in said end position. 
     
     
       23. The method of generating a check bit to establish orthogonal symmetry in a set of data and check signal bytes, each byte having N-1 bits and the set having N bytes, N being a positive integer greater than 1, including the following steps:   arranging the signals in a rectangular array;   selecting one of the diagonals of said rectangular array as a line of symmetry;   selecting a bit position of said check byte for a check bit signal to be generated;   generating the selected check bit signal by modulo 2 adding signals in the array along selected ones of diagonals transverse to said line of symmetry, the signals on said transverse diagonals being either on said line of symmetry or symmetrically disposed with respect to said line of symmetry and   selecting one of said selected diagonals in accordance with the location of said selected check bit signals in said array and adding said signals symmetrically except for said check bit signal to be generated.   
     
     
       24. The method of claim 23 including generating the seleceted check bit signal by modulo 2 ending all signals along said selected transverse diagonals except said check bit signal in one of said selected diagonals. 
     
     
       25. The method of claim 23 further including the step of selecting said check bit position and then selecting all said transverse diagonals in a sequence proceeding from said one transverse diagonal in but one direction along said line of symmetry. 
     
     
       26. Error correcting apparatus for processing data and check bit signals received from a multichannel signal transfer system, said signals in said channels being grouped into multichannel signal sets having a number of signals along each channel equal to the number of channels, all signals in one channel being a first check bit redundancy portion and one signal of each set in each remaining channel being a signal in a second check bit redundancy portion, said data signals and second check bit redundancy signals exhibiting orthogonal symmetry, the improvement including in combination;   first byte signal processing means for calculating said first check bit redundancy based on received signals from said remaining channels and comparing same with received first check bit redundancy signals from said one channel to supply first syndrome signals;   second byte signal processing means for each signal set for simultaneously processing one signal from each of said remaining channels to compute said second check bit redundancy and compare a received second redundancy signal with calculated second check bit redundancy to supply second syndrome signals;   means storing received signals from said remaining channels;   means receiving said syndrome signals and having orthogonally symmetrical matrix multiplication means to generate an error pattern for signals in error along any one of said channels in one of said signal sets; and   means receiving said stored signals and said error pattern for correcting signals in error, if any, along one or more of said channels.   
     
     
       27. The error correcting apparatus set forth in claim 26 including forward signal processing indicating means and backward signal processing indicating means; means in said second byte signal processing means responsive to said forward processing indicating means to premultiply said data signals on a byte basis by a matrix T based upon a polynomial for said second check bit redundancy portion and effectively forward shifting said signals to multiply by said matrix T and including linear feedback means during said second byte signal processing;   means in said second byte signal processing means responive to said backward byte processing indicating means to premultiply said data signals by the matrix T 7  and further having means operating said second byte signal processing means for effectively shifting said signals in a backward direction such that each shift is equal to a matrix multiplication of T -1  ; and   all of the other means in said error correcting apparatus being responsive to said forward and backward indicating means, respectively, to alter operations to accommodate forward and backward signal processing.   
     
     
       28. The apparatus set forth in claim 27 further including means in said syndrome receiving means indicating when said one channel is in error and operation altering means responsive to indicating that said one channel is in error not to correct said one channel; and means generating an indication of which data channel is in error and said error correcting means being jointly responsive to said second byte signal processing means and said error pointer means to correct data signals in error independent of signals from said one channel.   
     
     
       29. The error correcting apparatus set forth in claim 26 wherein said second byte signal processing means generates a set of output signals equal to T -i  S 2  ; error pattern generator means responsive to said T -i  S 2  and to said first byte signal processing means for generating a given error pattern;   counter means responsive to the number of bytes being processed to supply an R count;   code pointer generator means jointly responsive to said R count and said given error pattern to generate a track-in-error pointer signal;   error track parameter generator responsive to said code pointer generator and having error pointer means for generating a set of track-in error pointer signals and error correcting means jointly responsive to said given error pattern and to said track-in-error indicator to correct errors along a given channel wherein said given error pattern is used both to indicate a track in error and the error pattern along such track; and   wherein said error correction means is further responsive to said first byte signal processing means to correct a second channel in error in accordance with pointer signals received from said error track parameters generator.   
     
     
       30. An error correction signal generating system for a multichannel digital transfer system, a first plurality of said channels transferring data representing digital signals, the improvement including in combination:   means grouping data representing digital signals along each channel in signal groups having a number of signals equal to a number less than said first plurality;   means associating all groups in said channel together as a multichannel signal set;   means calculating check bit redundancy signals for all signals in one signal set;   means for transmitting a first portion of said redundancy signals along a channel not in said first plurality of channels and means for transmitting a second portion of said redundancy signals as one signal in each of said first plurality of channels; and   said calculating means establishing an orthogonal symmetry between said data signals and said second portion of said redundancy signals in each said signal set.   
     
     
       31. A signal transfer system having error detection and correction capabilities, including in combination: a signal transfer apparatus having a given error mode;   data signal means connected to said apparatus for exchanging data signals therewith;   first means interposed between said apparatus and said data signal means for selecting a given number of said data signals and including means grouping said selected data signals into a plurality of channel bytes to form an error correcting signal set;   error signal means in said first means receiving said data signals as cross-channel signal bytes, such cross-channel bytes having one data signal from each said channel bytes in accordance with a rectangular array of signals having one more signal along one dimension of said array than another dimension, redundancy means in said error signal means generating a redundancy signal byte having a number of check bit signals equal to the number of signals along said one dimension and operating on said signals as a square signal array with said redundancy signal byte in said array being parallel to said another dimension, means in said redundancy means relating each of said check bit signals to a unique group of said data signals such that all related signals (each check bit signal and its associated unique group of said data signals) exhibit orthogonal symmetry about a predetermined diagonal of said square array; and   means in said first means exchanging a redundancy signal byte between said error signal means and said apparatus.   
     
     
       32. The system set forth in claim 31 further including second error signal means in said first means for each signal set independently generating a separate second check bit signal on all signals in each said cross-channel bytes, plus a second check bit signal on said redundancy byte; and means exchanging all said second check bit signals between said signal transfer apparatus and said second error signal means.   
     
     
       33. The system set forth in claim 32 including error correction means receiving said data signals, said redundancy byte, and all said second check bit signals and for each said signal set for combining same to generate signals pointing to at least one of said bytes as being in error, if in error, and error pattern means selecting said redundancy byte exchanged with said signal transfer apparatus to indicate which bits of said byte in error are in error. 
     
     
       34. The method of arranging data signals and generating check redundancy signals in connection with transferring digital data signals, including the steps of: dividing said digital data signals into successive signal sets, dividing each said signal set into a given plurality of channel bytes, the number of said digital data signals in each channel byte being one less than said given plurality;   generating a first check redundancy signal byte having a number of signals equal to said given plurality and based upon a given error correcting polynomial of the irreducible type;   generating a second check redundancy signal byte to have said given plurality of byte check bit signal portions, selecting signals from each said channel bytes and said first check redundacy signal byte to generate said check bit signal portions, respectively; and   transferring said signal set and said first and second check redundancy signal bytes as a set of digital signals.   
     
     
       35. The method set forth in claim 34 further including the steps of: taking transferred signals and generating new first and second check redundancy signal bytes therefrom; and   combining transferred first and second check redundancy signal bytes with said new first and second check redundancy signal bytes to generate pointer signals pointing to bytes in error and error pattern signals pointing to individual transferred data signals in said bytes in error for enabling correction of said individual signals.   
     
     
       36. The method set forth in claim 35 further including the steps of evaluating signal transfer and pointing to bytes possibly being in error based upon such evaluation; and selectively modifying said combining of said check redundancy signal bytes in accordance with said error possibility pointing for correcting a greater number of signals than without such error pointing.   
     
     
       37. The method of preparing digital signals for recording such digital signals comprising the steps of: selecting a set of digital signals to be recorded, dividing said set into a given number less one of channel bytes, each channel byte having said given number of digital signals;   generating a check byte of said given number of signals in an orthogonal symmetrical manner for each digital data signal set;   independently generating a second check byte having an independent portion for groups of signals having one signal from each said channel byte and one portion for said check byte; and   recording all signals of one set including said check bytes as a separate record entity.   
     
     
       38. The method of reading correcting errors in digital signals read from a record member having recorded digital signals arranged in sets, each set having a predetermined number of digital data signals, a first redundancy signal subset exhibiting orthogonal symmetry with said digital signals in said set and a second redundancy signal subset in said set not exhibiting said orthogonal symmetry with said digital data signals but exhibiting a second error correcting characteristic, reading said signals from said record member, the method including the steps of:   generating new first and second redundancy signals from digital data signals read from said record member, such new redundancy signals matching recorded redundancy signals in an error-free condition;   comparing said new first and second redundancy signals with first and second redundancy signals read from said record member and generating an error location signal from said comparison showing that such error, if any, is in a given group of signals and error pattern signals showing which signals in such group are in error; and   changing the signals in error.   
     
     
       39. The method of preparing digital data signals for recording in a block of such signals in a multitrack record member, the method improvement including the steps of: 1. selecting a set of data signals to be recorded with one signal in each channel for forming a cross-channel byte;   2. arranging said bytes into sets of one less than the number of channels of said cross-channel bytes;   3. generating a check cross-channel byte on said set of cross-channel bytes;   4. recording said cross-channel bytes of (2) and (3); and   5. repeating (1)-(4) until all signals to be recorded in a block have been recorded.     
     
     
       40. The method of claim 39 further including the steps of generating a parity signal for each cross-channel byte independent of said check cross-channel byte generating indicating parity on such check cross-channel byte and recording such parity signals in one channel. 
     
     
       41. The method of correcting signals in error in a set of digital data signals; including the steps of: arranging the signals in a rectangular array of channel bytes along a first array dimension and cross-channel bytes along a second array dimension;   generating a check byte redundancy by successive byte calculations along one array dimension;   generating a first set of syndrome signals and error pattern signals from said redundancy and data signals along said one array dimension; and   correcting errors by applying said error pattern signals to data signals in one byte extending along a second one array dimension.   
     
     
       42. The method set forth in claim 41 further including the steps of: generating a second redundancy along said second one array dimension independently of said first redundancy but having a check portion based upon said first redundancy;   generating a second set of syndrome signals based upon said second redundancy and said data signals and said first redundancy, and a second set of error pattern signals; and   simultaneously applying said error patterns to two bytes, respectively, extending along said second one array dimension.   
     
     
       43. The method set forth in claim 42 and practiced in part in a linear feedback shift apparatus, the method of arranging said signals into said array including loading said bytes along said one array dimension serially into said shift register while synchronously shifting same and feeding back in accordance with a selected irreducible polynomial;   storing said loaded bytes fed to said shift register in a storage apparatus; and   applying said error pattern signals serially to selected two signals in each said loaded bytes while synchronously transferring such bytes from said storage apparatus.   
     
     
       44. A code circuit for a multichannel signal processing apparatus which processes a given number of signals from each channel as a group of signals, a check character set of signals being included in said group of signals and having one signal in each said channels, a multichannel network realizing polynomial g(x) and receiving said given signals in seriatim from said apparatus, one signal at a time from each channel in parallel with one signal from others of said channels after generating a syndrome character representative of errors in said given signals;   first means indicating a single channel in error,   means responsive to said indication for applying said syndrome character to said channel in error as an error pattern for correcting said given signals in said channel in error.   
     
     
       45. The circuit set forth in claim 44 further including a parity channel in said apparatus having a given number of parity signals associated with said group of signals, the improvement further including in combination: second means in said first means indicating two channels in error and means inhibiting said first means indications when two channels in error are indicated, and   means receiving said parity signals and said given signals to generate a parity syndrome character,   means responsive to said second means to apply said syndrome characters as error patterns to respective ones of said two channels in error for correcting signals in said channels in error.   
     
     
       46. Code circuits for multichannel signal apparatus, including in combination: a check character generator circuit means realizing polynomial g(x) and generating a check character based upon received signals from all channels and means supplying said check character with one signal in each of said channels,   first circuit means supplying successive sets of signals in parallel to said generator circuit,   second circuit means responsive to a given number of said successive sets of signals being supplied to activate transfer of said check character as a check set of signals interleaved among said sets,   control means for repeatedly activating said circuit means to generate a train of signal sets in all channels including interleaved check sets, and   receiver means responsive to said check sets and associated ones of said sets of signals to correct signals in any one of said channels. .Iadd. 47. Apparatus for identifying and correcting errors in one or two tracks of digital information derived from a multi-track medium, bits of data from ones of the tracks forming a byte, said tracks including a parity track, said bytes including n data bytes D 1  -D n  and an error checking code ECC byte of i bits, said error checking code ECC being related to said data bytes according to the relation ##EQU8##.Iaddend. comprising:   logic means for operating sequentially upon each of n received data bytes and an ECC byte to produce an error term E, said error term being equal to zero in the absence of errors in the received data and ECC bytes;   second logic means for regressively operating upon said error term -i times to produce the vector EC -i  ;   means for accepting signals representative of data bits of the digital information and responsive thereto for deriving a parity character P n  which in combination with a data byte D n  produces an even number of data bits of a first kind;   combining means for logically combining a regressed error vector and a parity vector P n  on a bit-by-bit basis to form the expression EB -i  +P n  ;   a data correction matrix;   parity correction logic means coupled to said logic means and to said means for accepting for receiving an error vector and a parity vector and operative to apply a signal to said data correction matrix to correct the ith data track to conform with said parity vector when said regressed error vector equals said parity vector;   means for receiving track pointers indicating the presence of errors in ones of said tracks and for disabling the correction apparatus when three or more tracks are in error;   track separation logic means coupled to said means for receiving and responsive to track pointers for identifying the separation (i-j) between a most significant track i which is associated with a lower-order polynomial term and a least significant track j which is associated with a higher-order polynomial term of the polynomial   m=1       n=7       ΣD.sub.n X.sup.m       m=7       n=1     a divisor generator coupled to said track separation logic for selecting the term 1+B - (i-j) in accordance with track separation (i-j);     dividend logic means for dividing said regressively operated vector by the output of said divisor generator to produce an error vector e nj  for data in the least significant track j in error;   logic means for combining on a bit-by-bit basis said derived parity character P n  and said error vector e nj  to produce an error vector e ni  for data in the most significant track i in error;   means for associating said error vectors e ni  and e nj  with the data tracks i and j respectively; and   said data correction matrix receiving uncorrected data and said error vectors and combining said data and said vectors to invert the polarity of erroneous bits of said uncorrected data in accordance with the   
     
     
        characteristics of said error vectors.  .Iadd. 48.  The invention defined in claim 47, further including: means for receiving a pointer indicative of an error in a received parity track P; and   means for correcting said parity track to correspond to said error vector e ni . .Iaddend. .Iadd. 49. Apparatus for identifying and correcting errors in one or two tracks of digital information derived from an encoded medium, said tracks including a parity track, each track being encoded with bits, each bit being associated with another bit from each track to form a byte, said bytes comprising data bytes D 1  -D n  and an error checking byte ECC, said error checking byte being related to said data bytes according to the relation ##EQU9##.Iaddend. comprising:   first logic means for operating sequentially upon each of n received data bytes and the error checking byte according to an operator B to produce an error term E, said operator B being such as to produce the error checking byte by sequentially operating upon data bytes D 1  -D n  said error term being equal to zero in the absence of errors in the received data and error checking bytes;   second logic means for regressively operating i times upon said error term according to the operator B to sequentially produce error vectors e nl  through e ni  ;   means responsive to bits encoded on the parity track of the digital information for generating parity vectors P n  which when combined with a received byte and associated parity term produce an even number of data bits of a first kind;   means for sequentially combining ones of said error vectors with ones of said parity vectors;   separation logic means for receiving track pointers indicating the existence of errors in two identifiable tracks and producing output signals in response thereto;   track separation logic means coupled to said separation logic means and responsive to said output signals for identifying the separation between the most significant and least significant tracks in error;   divisor generator means coupled to said track separation logic means for outputting a divisor expression;   means for dividing ones of the combined error vector e ni  and parity vector by said divisor expression to produce an error vector for data in the least significant track in error;   means for additively combining said least significant track error vector and said parity vector to produce an error vector for data in the most significant track in error; and   a matrix for associating each of said error vectors with appropriate ones of said tracks in error and for correcting erroneous data bits in said   
     
     
        tracks in accordance with said error vectors.  .Iadd. 50.  Apparatus as set forth in claim 49, further including sequence inversion means coupled to said first logic means for inverting the order in which tracks of data bits are received by said first logic means. .Iaddend..Iadd. 51. Apparatus as defined in claim 50, further including means for rendering said identifying and correcting apparatus inoperative when track pointers indicating errors in three or more tracks are present. .Iaddend..Iadd. 52. Apparatus as defined in claim 51, further including means for receiving a pointer indicative of an error in a received parity track; and means for correcting said parity track in conformity with the error vector for said most significant track in error. .Iaddend. .Iadd. 53. Apparatus as defined in claim 52, wherein said matrix for associating includes a first plurality of inputs, further including:   means for sequentially applying bytes of uncorrected received data to said first plurality of inputs;   said matrix for associating comprising a data correction matrix including said first plurality of inputs and further having a second plurality of inputs, one input for each data track;   a most significant track correction vector matrix having a plurality of outputs coupled to said second plurality of inputs, and having inputs coupled to said means for additively combining and to said means for identifying said most significant track in error, for combining an error vector signal and a track identification signal and outputting a correction signal upon one of said outputs coincidentally with the transfer of a byte having an erroneous data bit in the most significant track in error to said data correction matrix; and   a least significant track correction vector matrix having a plurality of outputs coupled to said second plurality of inputs, and having inputs coupled to said means for dividing and to said separation logic, for combining an error vector signal and a track identification signal and outputting a correction signal upon one of said outputs coincidentally with the transfer of a byte having an erroneous data bit in the least significant track in error to said data correction matrix. .Iaddend. .Iadd. 54. The method of identifying and correcting errors in one or two tracks of digital information derived from an encoded medium, said tracks including a parity track, each track being encoded with bits, each bit being associated with another bit from each track to form a byte, said bytes including n data bytes and an error checking code byte, comprising:   operating n+1 times upon n sequentially received data bytes and an error checking code byte in accordance with the operator B, said operator B being that operator used to develop the ECC byte in the encoded data, to produce an error term E;   generating a local parity signal to provide an even number of data bits of a first kind for each received data and error checking code byte including a received parity bit;   regressively operating upon error term E with the operator B a number of times i to sequentially produce error vectors e n1  -e ni  ;   combining each sequentially produced error vector with ones of said parity vectors;   detecting a coincidence between an error vector and a parity vector; and   correcting the track of received data whose position corresponds to the number of regressive operations needed to achieve correspondence between said error and parity vectors, in accordance with the error vector so   
     
     
        achieved. .Iaddend..Iadd. 55.  The method defined in claim 54, further including the steps of detecting the occurrence of n+1 regressive operations in which no coincidence between an error vector and a parity vector has occurred;   detecting the presence of two tracks of received data in which errors may have occurred and identifying the tracks;   dividing the combined error vector e ni  for the most significant track in error and the associated parity vector by a term which is a function of the separation of the two tracks in error to produce an error vector e nj  for the least significant of said tracks;   associating the least significant track error vector e nj  with the least significant track in error;   associating the most significant track error vector e ni  with the most significant track in error; and   correcting the erroneous tracks in accordance with said error vectors.   
     
     
        .Iaddend..Iadd. 56.  The method defined in claim 55, wherein i represents the position of the most significant track in error and j represents the position of the least significant track in error wherein the term by which combined error and parity vectors are divided is   1+B.sup.(-i-j).     .Iaddend..Iadd. 57. The methd defined in claim 56, further including the step of detecting the presence of three or more tracks in error and preventing the correction of any of said tracks. .Iaddend..Iadd. 58. The method defined in claim 57, wherein said error vectors each comprise at least n bits, which bits are sequentially compared with corresponding bits in a given track of received data. .Iaddend.