Integrating analog-to-digital converter having digitally-derived offset error compensation and bipolar operation without zero discontinuity

Abstract

An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. The integrator first is ramped up and then back to a reference level, by sequential application of opposite-polarity reference signals. A digital determination of net offset error then is made by comparing the total time of ramp-up-and-back with a fixed time period set by a clock generator. During the subsequent conversion operation, integration of the analog signal is controlled in accordance with the amount of net offset error so as to provide a feed-forward error correction. Integration is always in the same direction away from zero for analog signals of either polarity, thus avoiding the effects of discontinuity around zero input.

I claim: 
     
       1. An analog-to-digital converter comprising: an integrator arranged to produce ramp signals at rates corresponding to the magnitude of signals applied to the input thereof, the ramp direction being determined by the polarity of the applied signal;   means to condition said integrator to start integrating from a predetermined output datum level at a start time;   means to supply reference signals of opposite effective polarity for application to the input of said integrator;   clock means for producing clock pulses and successive timing control pulses following said start time;   switch means for applying signals to the input of said integrator;   first means to operate said switch means at said start time to apply to said integrator one of said reference signals in a given polarity to cause said integrator to ramp away from said datum level for a first time period as measured by said clock means;   second means to operate said switch means subsequent to said first time period to apply to the input of the integrator one of said reference signals of polarity opposite to said given polarity to cause said integrator to ramp back towards said datum level during a second time period;   a comparator coupled to the output of said integrator for producing a compare signal when said integrator output returns to said datum level, thereby signalling the end of said second time period;   third means responsive to the development of said compare signal at the end of said second time period for activating said switch means to apply to said integrator input for a third time period a composite signal including one of said reference signals and the unknown analog signal which is to be converted to a digital signal, said third time period being terminated upon the occurrence of a first one of said timing control pulses;   means operable at the termination of said third time period for applying to the input of said integrator one of said reference signals of polarity opposite to that of said composite signal, thereby to ramp said integrator output back towards said datum level during a fourth time period; and   digitizing means coupled to the output of said comparator and to said clock means for producing an output digital signal representing the number of clock pulses occurring between the appearance of a second one of said timing control pulses and the development by said comparator of a compare signal signalling the end of said fourth time period.   
     
     
       2. Apparatus as claimed in claim 1, wherein said reference signals are of equal magnitude. 
     
     
       3. Apparatus as claimed in claim 1, including means to produce an error signal indicating the difference in time between the end of said second time period and the occurrence of a third timing control pulse preceding said first timing control pulse; and means responsive to said error signal for controlling the timing of occurrence of said first timing control pulse so as to minimize the output error due to changes in effective gain of the converter.   
     
     
       4. Apparatus as claimed in claim 3, wherein the time duration of said first time period is equal to the time between the beginning of said second time period and the occurrence of said third timing control pulse. 
     
     
       5. An analog-to-digital converter comprising: an integrator arranged to produce ramp signals at ramp rates corresponding to the magnitude of signals applied to the input thereof, the ramp direction being determined by the polarity of the applied signal;   means to condition said integrator to start integrating from a predetermined datum level;   means to supply reference signals of opposite effective polarities for application to the input of said integrator;   clock means for producing clock pulses;   switch means for applying signals to the input of said integrator;   first means to operate said switch means to aply to said integrator one of said reference signals in a given polarity for a first time period as measured by said clock means;   second means to operate said switch means subsequent to said first time period to apply to the input of said integrator one of said reference signals of polarity opposite to said given polarity to cause said integrator to ramp back towards said datum level during a second time period;   a comparator coupled to the output of said integrator for producing a compare signal when said integrator output returns to said datum level, thereby signalling the end of said second time period;   third means to operate said switch means to apply signals to the input of said integrator for two additional successive time periods with the signals applied thereto being of different polarity;   said third means including means to apply the unknown analog signal to said integrator input during one of said additional time periods, and to apply a reference signal to said integrator input during the other time period;   said third means further including means to adjust the duration of said one additional time period in accordance with the amount of time between the occurrence of said compare signal, at the end of said second time period, and the occurrence of a predetermined clock produced by said clock means; and   digitizing means coupled to the output of said comparator and to said clock means for producing an output digital signal representing the magnitude of said unknown analog signal in accordance with the integral signal developed by said integrator during said one additional time period.   
     
     
       6. Apparatus as claimed in claim 5, wherein said reference signals are of equal magnitude; said first time period being equal in duration to the time between the beginning of said second time period and the occurrence of said predetermined clock pulse.   
     
     
       7. In an analog-to-digital converter wherein an electronic integrator is operated through a cycle of two successive time periods so as to ramp in one direction away from a datum level and then return to the datum level, the unknown analog signal being applied as an input to the integrator during at least one of said time periods so that the integration action during that one period is responsive to the magnitude of the unknown signal; there further being included clock means for determining time durations and for developing digital output signals responsive to the magnitude of integrated output produced by the integrator with the unknown analog signal applied thereto for a particular period of time; that improvement, for minimizing the effects of offset errors and the like occurring in the integrator and/or associated circuitry, which comprises:   means to condition said integrator to start integrating from a predetermined datum level at a start time;   a source of reference signals of opposite polarities for application to said integrator;   switch means for applying signals to the input of said integrator;   first means to operate said switch means to apply a reference signal to said integrator in a given polarity for a first predetermined fixed time period;   second means to operate said switch means subsequent to said first time period to apply to the input of said integrator a reference signal of polarity oposite to said given polarity to cause said integrator to ramp back towards said datum level during a second time period;   a comparator coupled to the output of said integrator for producing a compare signal when said integrator output returns to said datum level, thereby signalling the end of said second time period;   means operable thereafter to cycle said converter through said two successive time periods for producing a digital output; and   means for adjusting the integration action of said integrator during said one of said two successive time periods in accordance with changes in the length of time between the development of said compare signal and the end of a second predetermined fixed time period following said first fixed time period.   
     
     
       8. Apparatus as claimed in claim 7, wherein said adjusting means comprises means to alter the time duration of said one of said two successive time periods. 
     
     
       9. Apparatus as claimed in claim 8, wherein said unknown analog signal is applied to said integrator during the first of said two successive time periods; said adjusting means comprising means responsive to said compare signal for starting said first of said successive time periods; and   means responsive to said clock means for ending said first of said successive time periods.   
     
     
       10. Apparatus as claimed in claim 9, including means responsive to said length of time between the development of said compare signal and the end of said second fixed time period for selecting a particular clock pulse for ending said first of said successive time periods. 
     
     
       11. Apparatus as claimed in claim 7, wherein said adjusting means comprising means responsive to the number of clock pulse occurring between said compare signal and the end of said second fixed time period, whereby to provide a digital adjustment of the integration action. 
     
     
       12. An analog-to-digital converter comprising: an integrator;   means to operate said integrator from a start time through an operating cycle comprising two successive time periods where the integrator is caused to ramp first in one direction for a predetermined time duration, and then to ramp in the opposite direction;   means to apply to the integrator input during the first period, of predetermined duration, a reference signal of one polarity together with an unknown analog signal for a predetermined time duration;   means to apply to the integrator during the second period a reference signal of polarity opposite to said one polarity, thereby to ramp said integrator in the opposite direction back towards said datum level;   a comparator coupled to the output of said integrator to produce a compare signal when the output of the integrator returns to said datum level;   clock means for developing a timing control pulse at a predetermined time subsequent to the end of said first time period; and   digitizing means coupled to said clock means and controlled by said comparator output to produce a digital output signal representing the number of clock pulses between said timing control pulse and the occurrence of said compare signal.   
     
     
       13. Apparatus as claimed in claim 12, including; initializing circuit means operable prior to said start time to set the output of said integrator at a level which is offset from said datum in said one direction;   said initializing means including means to ramp said integrator in said opposite direction, towards said datum level;   signal-producing means responsive to the output of said comparator when said integrator output reaches said datum level in response to the operation of said initializing means, to produce a start signal to signify the start time for said converter; and   means operable by said start signal for activating said converter through said operating cycle.   
     
     
       14. Apparatus as claimed in claim 13, including; pre-conditioning means responsive to said start signal to operate said integrator through a conditioning cycle preceeding said operating cycle;   said pre-conditioning means including means to apply a reference signal of one polarity to said integrator to cause it to ramp in said one direction away from said datum level for one conditioning time period and thereafter to apply a reference signal of opposite polarity to cause it to ramp back to said datum level in said opposite direction for a second conditioning time period; and   means responsive to the output of said comparator, when said integrator output reaches said datum level, for initiating said operating cycle.   
     
     
       15. Apparatus as claimed in claim 14, wherein said pre-conditioning means includes means to activate the function of said clock means at the beginning of said conditioning cycle; and means responsive to a particular clock pulse from said clock means for terminating said first operating time period, whereby the time duration of said first operating time period is affected by the length of time between said start signal and the time of said compare signal at the end of the second conditioning time period.   
     
     
       16. Apparatus as claimed in claim 15, including means for developing an error signal responsive to the time difference between the occurrence of said compare signal, at the end of said second conditioning time period, and the end of a fixed time period following the start of said second conditioning time period; and control means responsive to said error signal for selecting the time of said particular clock pulse which terminates said first operating time period.   
     
     
       17. Apparatus as claimed in claim 16, wherein said first conditioning-time period encompasses K 1  clock pulses, said fixed time period thereafter also encompasses K 1  clock pulses, and there are n clock pulses between the occurrence of said compare signal and the end of said fixed time period; said control means serving to set at K 1  + n/2 clock pulses the length of said first operating time period and the length of the period between the start of said second operating time period and the occurrence of said timing control pulse following the start of said second operating time period.   
     
     
       18. In the art of transforming an unknown analog signal into a corresponding digital signal wherein a converter is operated through a measurement cycle comprising a measurement time period during which the unknown analog signal is applied to an integrating circuit to cause the integrating circuit to ramp away from a datum level at a ramp rate related to the analog signal magnitude and a clock generator is operated to produce a digital signal responsive to the amount of accumulated integration during that time period; the improvement for minimizing the amount of error resulting from offset, and the like, in the integrating circuit, comprising the method of operating the integrating circuit prior to the application of said unknown analog signal by:   applying a reference signal having a given polarity to said integrating circuit for a first preliminary time period to cause said integrating circuit output to ramp away from a datum level;   applying to said integrating circuit during a second preliminary time period, following said first time period, a second reference signal having a polarity opposite to said given polarity to return the said integrating circuit output back to said datum level; and   thereafter operating said integrating circuit through said measurement cycle with the integration action thereof controlled in accordance with the length of time between said return of said integrating circuit output to said datum level and the end of a predetermined time period following the end of said first time period to compensate for changes in offset error .Iadd.and the like .Iaddend.evidenced by said length of time.   
     
     
       19. The method of claim 18, wherein said integration action during said measurement cycle is controlled by adjusting the length of time of said measurement time period. 
     
     
       20. The method of claim 18, wherein said first and second time periods are of pre-set (fixed) duration; said integration action being controlled by starting said measurement time period in response to the return of said integration circuit output to said datum level, and ending said measurement time period at a predetermined time duration following the end of said second preliminary time period.   
     
     
       21. The method of claim 20, wherein said predetermined time duration is automatically controlled in accordance with the length of time between said return of said integrating circuitry to said datum level and the end of said predetermined time period following the end of said first time period. 
     
     
       22. In an analog-to-digital converter of the type having an integrator adapted to be ramped up-and-back in one polarity region with respect to a datum level by applying to said integrator successive signals including at least one reference signal and the unknown analog signal; comparator means coupled to the integrator output to detect when the output signal has returned to datum level; clock-pulse means for measuring time intervals and developing the desired digital number; control circuit means for controlling the functioning of the integrator and the clock-pulse means; and means coupling the output of said comparator means to said control circuit means for applying thereto a controlling logic signal when said integrator output reaches datum level at the end of said down-ramp during the conversion operation; that improvment in said converter comprising:   first means operable prior to a conversion operation to set the integrator output at a predetermined level which is offset from said datum level in the same polarity region as said up-and-back ramp;   second means responsive to a start signal for causing said integrator output to ramp from said predetermined level towards said datum level; and   third means responsive to the output of said comparator means when said integrator output reaches datum level while under control of said second means, said third means including means for initiating a conversion operation.   
     
     
       23. Apparatus as claimed in claim 22, wherein said third means includes means to initiate a count of clock pulses from said clock-pulse means. 
     
     
       24. Apparatus as claimed in claim 22, wherein means are included to produce said up-ramp by applying thereto said unknown analog signal and to produce said down-ramp by applying said reference signal to said integrator. 
     
     
       25. Apparatus as claimed in claim 24, wherein said second means comprises means for applying said reference signal to said integrator to ramp the integrator output towards said datum level at the same ramp-rate as the down-ramp during the conversion operation. 
     
     
       26. Apparatus as claimed in claim 22, wherein said third means comprises means to operate said integrator first through a pre-conversion cycle in which the integrator is ramped up-and-back by successive, opposite-polarity reference signals for the purpose of determining the net error in the system, and then to operate said integrator through a conversion cycle in which the integrator is ramped up by the unknown analog signal and then back to datum by the same reference signal applied to the integrator for producing ramp-back during said pre-conversion cycle. 
     
     
       27. Apparatus as claimed in claim 26, wherein said second means includes means to apply said same reference signal to said integrator to cause it to ramp towards datum, whereby the ramp-back towards datum is always at the same rate for all functions of said integrator, so as to minimize errors due to response time of the comparator means. 
     
     
       28. In the art of transforming an unknown analog signal into a corresponding digital signal wherein during a measurement cycle the unknown analog signal and a reference signal are controllably applied to an integrator to cause its output to ramp first in one direction away from a datum level and then to ramp back towards said datum level, there being also included clock-pulse means for timing the operation of the integrator and for producing a digital output signal according to time measurements indicating the magnitude of said unknown analog signal as reflected by the amount of accummulated integral during the period said integrator is operated under control of said unknown analog signal; the improved technique for reducing the amount of error in said output signal resulting from system offsets and the like comprising the method of operating said integrator through a pre-conversion cycle prior to said measurement cycle wherein reference signal means without said unknown analog signal are applied to said integrator so as to cause the output thereof to ramp away from datum level and then to ramp back to said datum level to develop a digital measure of offset error as indicated by the clock-pulse time between (1) the time of return to said datum level and (2) a predetermined time following start of said pre-conversion cycle; and   thereafter operating said integrator through said measurement cycle with the integration action thereof controlled in accordance with said clock-pulse time developed during said pre-conversion cycle so as to alter the digital output signal in correspondence to the amount of offset error.   
     
     
       29. The method of claim 28, wherein said integration action during said measurement cycle is controlled by adjusting the length of time said unknown analog signal is applied to said integrator. 
     
     
       30. The method of claim 28, wherein during said measurement cycle the ramp-up of said integrator is produced by applying said unknown analog signal to said integrator and said ramp-back is effected by applying a reference signal to the integrator, the digital output signal being developed in accordance with the number of clock pulses between (1) the return to datum during said measurement cycle and (2) a reference time following the start of said measurement cycle; said integration action being controlled at least in part by starting said measurement cycle in response to the return of said integrator output to datum level at the end of said pre-conversion cycle, and ending said measurement time period at a predetermined time duration following the end of said pre-conversion cycle.   
     
     
       31. The method of claim 30, wherein said time duration is determined by said clock-pulse time developed during said pre-conversion cycle, whereby the integration action is controlled by adjusting both the start and ending times of integration of said analog signal in accordance with the digitally measured offset error. 
     
     
       32. The method of claim 30, including the step of automatically controlling the time duration between the end of said ramp-up during the measurement cycle and the occurrence of said reference time, in response to the clock-pulse time, previously determined during said pre-conversion cycle. 
     
     
       33. The method of claim 30, wherein the ramp-up during said pre-conversion cycle is produced by applying a reference signal to said integrator for a fixed period of time. .Iadd. 34. A method of transforming an unknown analog signal into a corresponding digital signal wherein during a measurement cycle the unknown analog signal and a reference signal are controllably applied to an integrator to cause its output to ramp first in one direction away from a datum level and then to ramp back to said datum level, there being also included clock-pulse means for timing the operation of the integrator and for producing a digital output signal according to measurements by said clock-pulse means of the time difference between (a) the time said integrator output returns to datum level and (b) a reference time, said time difference indicating the magnitude of said unknown analog signal as reflected by the amount of accummulated integral during the period said integrator is operated under control of said unknown analog signal, and wherein, for reducing the amount of error in said output signal resulting from system offsets, said integrator first is operated through a pre-conversion cycle prior to said measurement cycle wherein reference signal means without said unknown analog signal are applied to said integrator so as to cause the output thereof to ramp away from the datum level and then to ramp back to said datum level to develop a digital measure of an error as indicated by the clock-pulse time between (1) the time of return to said datum level and (2) a predetermined time following start of said pre-conversion cycle; and said integrator thereafter is operated through said measurement cycle with said time difference being determined not only in accordance with the value of said analog signal applied to said integrator but also in accordance with said clock-pulse time developed during said pre-conversion cycle so as to alter the digital output signal in correspondence to the amount of offset error. .Iaddend..Iadd. 35. The method claimed in claim 34, wherein said time difference is controlled by varying the integration action of said integrator during said measurement cycle in accordance with the clock-pulse time developed during said pre-conversion cycle. .Iaddend..Iadd. 36. The method claimed in claim 35, wherein said integration action during said measurement cycle is controlled by adjusting the length of time said unknown analog signal is applied to said integrator. .Iaddend. .Iadd. 37. Apparatus for transforming an unknown analog signal into a corresponding digital signal wherein during a measurement cycle the unknown analog signal and a reference signal are controllably applied to an integrator to cause its output to ramp first in one direction away from a datum level and then to ramp back to said datum level, there being also included clock-pulse means for timing the operation of the integrator and for producing a digital output signal according to time measurements by said clock-pulse means of the time difference between (a) the time said integrator output returns to datum level, and (b) a reference time, said time difference indicating the magnitude of said unknown analog signal as reflected by the amount of accumulated integral during the period said integrator is operated under control of said unknown analog signal; said apparatus comprising: first means for operating said integrator through a pre-conversion cycle prior to said measurement cycle wherein reference signal means without said unknown analog signal are applied to said integrator so as to cause the output thereof to ramp away from datum level and then to ramp back to said datum level to develop a digital measure indicated by the clock-pulse time between (1) the time of return to said datum level and (2) a predetermined time following start of said pre-conversion cycle; and   second means for operating said integrator through said measurement cycle while controlling said time difference both in accordance with the value of said analog signal applied to said integrator and in accordance with said clock-pulse time developed during said pre-conversion cycle so as to automatically adjust the digital output signal in correspondence thereto.   
     
     
        .Iaddend. .Iadd. 38.  In an analog-to-digital converter of the type having an integrator adapted to be ramped up-and-back in one polarity region with respect to a datum level by applying to said integrator successive signals including at least one reference signal and an unknown analog signal; comparator means coupled to the integrator output to detect when the output signal has returned to datum level; clock-pulse means for measuring time intervals; control circuit means for controlling the functioning of the integrator and the clock-pulse means; and means coupling the output of said comparator means to said control circuit means for applying thereto a controlling logic signal when said integrator output reaches datum level at the end of said down-ramp during the conversion operation; that improvement in said converter comprising:   first means operable prior to a conversion operation to offset the integrator output from said datum level in the same polarity region as said up-and-back ramp;   second means responsive to a start signal for causing said integrator output to ramp from its offset value towards said datum level; and   third means responsive to the output of said comparator means when said integrator output reaches datum level while ramping from said offset value, said third means including means for initiating a conversion   
     
     
        operation. .Iaddend..Iadd. 39.  Apparatus as claimed in claim 38, wherein the slope of the ramp from said offset value towards said datum level is equal to the slope of said down-ramp during said conversion operation. .Iaddend. .Iadd. 40. In an analog-to-digital converter of the type having an integrator adapted to be ramped up-and-back in one polarity region with respect to a datum level by applying to said integrator successive signals including at least one reference signal and an unknown analog signal; means to produce a start signal to initiate operation of the converter including such up-and-back ramp; comparator means coupled to the integrator output to detect when the output signal has returned to datum level; clock-pulse means for measuring time intervals; control circuit means for controlling the functioning of the integrator and the clock-pulse means; and means coupling the output of said comparator means to said control circuit means for applying thereto a controlling logic signal when said integrator output reaches datum level at the end of said down-ramp during the conversion operation; that improvement in said converter comprising:   first means operable prior to a conversion operation to offset the integrator output from said datum level to an arbitrary predetermined value in the same polarity region as said up-and-back ramp;   second means operable after said first means and responsive to said start signal while said integrator output is offset to said predetermined value for causing said integrator output to ramp from said offset value towards said datum level; and   third means responsive to the output of said comparator means when said integrator output reaches datum level while ramping back from said offset value in response to said start signal, said third means including means for initiating operation of said converter to carry out a conversion operation. .Iaddend. .Iadd. 41. Apparatus as claimed in claim 40, wherein the slope of the ramp from said offset value towards said datum level is equal to the slope of said down-ramp during said conversion operation. .Iaddend..Iadd. 42. Apparatus as claimed in claim 40, wherein said third means includes error-correction means to perform an error-correction function preceding said conversion operation;   said error-correction means including means to ramp said integrator up-and-back in a predetermined fashion in said one polarity region; and   means responsive to the output of said comparator when said integrator reaches datum level while ramping back while performing said error-correction function, to initiate said conversion operation. .Iaddend..Iadd. 43. Apparatus as claimed in claim 42, wherein the slope of the down-ramp of said integrator remains the same for: (1) the pre-operation down-ramp from said arbitrary offset value, (2) the down-ramp during said error-correction function, and (3) the down-ramp during said conversion operation.