Three output level logic circuit

Abstract

A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.

I claim: 
     
       1. In a logic circuit having first and second signal-receiving input means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal-receiving input means and to said output terminal for selectively switching between first and second conditions in response to application of a signal to the first signal-receiving input means to provide first or second output levels on said output terminal, and second switching means connected to said second signal-receiving input means and to said first switching means to cause said first switching means to assume a third condition in response to the application of a signal to said second signal-receiving input means to provide a third output level at said output terminal, said output terminal exhibiting a high impedance relative to said first and second output levels. 
     
     
       2. A logic circuit as in claim 1 where said output terminal at said first and second output levels serves as a current sink or current source and at said third output level said output terminal provides a high output impedance. 
     
     
       3. A logic circuit as in claim 1 in which said first switching means includes first and second output means coupled to said output terminal in which for one of said two output levels one of said output means is active and the other inactive and for said other of said two output levels the other of said output means is active and the one is inactive and in which for said third output level said second switching means inactivates both of said output means. 
     
     
       4. A logic circuit as in claim 3 in which said first and second output means includes first and second transistors respectively.Iadd., .Iaddend.said first transistor being coupled to a third transistor and said second transistor being coupled to a fourth transistor, said second switching means when said logic circuit is in said third output level providing a low impedance path-shunting current from an input terminal of said third transistor to inactivate said first transistor and in addition shunting current from an output terminal of said fourth transistor to inactivate said second transistor. .Iadd. 5. A system comprising a plurality of logic circuits as claimed in claim 1, a common line, and means connecting the respective output terminals of said plurality of logic circuits to said common line. .Iaddend. .Iadd. 6. In a logic circuit having first and second signal-receiving input means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal-receiving input means and to said output terminal for selectively switching between first and second conditions in response to application of a signal to the first signal-receiving input means to provide first or second output levels respectively at said output terminal, and second switching means connected to said second signal-receiving input means and to said first switching means to cause said first switching means to assume a third condition in response to the application of a signal to said second signal-receiving input means to provide a third output level at said output terminal, said third output level at said output terminal exhibiting a high impedance relative to said first and second output levels, said first switching means including first and second output means coupled to said output terminal such that to provide one of said first and second output levels one of said output means is rendered active and the other rendered inactive and to provide the other of said first and second output levels the other of said output means is rendered active and the said one is rendered inactive and such that to provide said third output level said second switching means inactivates both of said output means..Iaddend. .Iadd. 7. A logic circuit as claimed in claim 6, in which said first and second output means includes respectively first and second transistors having their main current paths connected in series, a third transistor coupled to said first and second transistors for selectively activating and inactivating said first and second transistors respectively in response to application of a signal to the first signal-receiving input means and for inactivating and activating said first and second transistors respectively in response to application of a different signal to the first signal-receiving input means, and means coupling said second switching means to both said first and second transistors to inactivate both said first and second transistors simultaneously in response to a signal applied to said second signal-receiving input means to provide said third output level. .Iaddend..Iadd. 8. A logic circuit as claimed in claim 7 wherein said means coupling said second switching means to both said first and second transistors includes said third transistor. .Iaddend..Iadd. 9. A system comprising a plurality of logic circuits as claimed in claim 7, a common line, and means connecting the respective output terminals of said plurality of logic circuits to said common line..Iaddend.