FET logic gate circuits

Abstract

A gate circuit includes field effect transistors interconnected to provide an output signal of a first type whenever all input signals are of predetermined types, and to provide an output of a second type whenever any input signal is other than one of the predetermined types, wherein the only current required by the circuit is that supplied by the output of the circuit to a load which is driven by the circuit. Preferably, the circuit includes a plurality of logic-steering field effect transistors connected with their controlled electrodes in series such that an input signal is connected to an output load device, such as a capacitor, only if all of the logic-steering transistors have been turned ON. A ground return transistor is provided for each logic-steering transistor and operates to provide a ground at the output of the logic-steering transistor if an improper input signal is received. Binary data signals, or inversions thereof, are connected to the gates of the transistors in desired patterns to operate the load device only on a proper combination of input signals.

What I claim is: 
     
       1. A gate circuit, which comprises: means for providing a signal on a first lead;   means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead;   means for transferring the signal on the first lead to a first output port in response to a second data signal of one type, and for transferring the signal on the third lead to the first output port in response to a second data signal of a second type;   means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead;   an output load impedance; and   means for transferring the signal at the first output port to the output load impedance in response to a third data signal of one type, and for transferring the signal on the fourth lead to the output load impedance in response to a third data signal of a second-type.   
     
     
       2. A gate circuit, as recited in claim 1, where the output load impedance is a capacitor. 
     
     
       3. A gate circuit, comprising: means for providing a first data signal on a first lead and an inversion thereof on a second lead;   means for providing a first constant voltage on a third lead and a second and different constant voltage on a fourth lead;   first and second field effect transistors each having a gate and a first and second controlled terminals;   means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the first lead, the second controlled terminal serving as a first output port;   means for connecting the second field effect transistor to the second and fourth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the second lead; and   means for connecting the second controlled terminal of the first field effect transistor to the second controlled terminal of the second field effect transistor.   
     
     
       4. A gate as recited in claim 3, further comprising: means for providing a second data signal on a fifth lead and an inversion thereof on a sixth lead;   third and fourth field effect transistors each having a gate and first and second controlled terminals;   means for connecting the third field effect transistor to the first output port and to the sixth lead, the first controlled terminal being connecting to the first output port and the gate being connected to the sixth lead, the second controlled terminal serving as a second output port;   means for connecting the fourth field effect transistor to the third and fifth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the fifth lead; and   means for connecting the second controlled terminal of the third field effect transistor to the second controlled terminal of the fourth field effect transistor.   
     
     
       5. A circuit as recited in claim 4, wherein the means for providing a first data signal on a first lead and an inversion of said first data signal on a second lead comprises a first phase splitting circuit, and wherein the means for providing a second data signal on a fifth lead and an inversion of the second data signal on a sixth lead comprises a second phase splitting circuit. 
     
     
       6. A gate circuit, comprising: means for providing a first data signal on a first lead;   means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead;   means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead;   first, second, third and fourth field effect transistors each having a gate and first and second controlled terminals;   means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the first lead and the gate being connected to the third lead, the second controlled terminal forming a first output port;   means for connecting the second field effect transistor to the second and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the second lead;   means for connecting the third field effect transistor to the fourth and fifth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the fifth lead, the second controlled terminal providing a second output port;   means for connecting the gate of the fourth field effect transistor to the fourth lead;   means for interconnecting the second controlled terminals of the first, second and fourth field effect transistors; and   means for connecting the first controlled terminal of the fourth field effect transistor to the second controlled terminal of the third field effect transistor.   
     
     
       7. A gate circuit as recited in claim 6 wherein the means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead comprises a first phase splitting circuit and wherein the means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead comprises a second phase splitting circuit. 
     
     
       8. A MOSFET coincidence gate circuit for producing an output signal to charge a capacitor only in response to one selected combination of a plurality of binary data signals, and for discharging the capacitor, if previously charged, for all other combinations of the data signals, which comprises: means for providing two input signals for each bit, one corresponding to the bit and one to its complement;   a plurality of logic-steering FETs ("LFs") arranged in a sequence, each of which has its gate connected to a first one of the input signals for an associated bit selected such that each LF becomes conductive only when the associated bit assumes the selected state;   means for supplying a capacitor-charging signal to a first controlled terminal of a first LF in the sequence, each subsequent LF having its first controlled terminal connected in series with the second controlled terminal of preceding LF, the output capacitor being connected to the second controlled terminal of the last LF in the sequence so that the capacitor is connected to the charging signal only whenever all of the LFs have been rendered conductive in response to the selected combination of the input signals; and   a plurality of ground-return FETs ("GFs") arranged in a sequence corresponding to that of the LFs, each of which has its gate connected to the second input signal for an associated bit such that each GF becomes conductive only when the associated bit assumes the nonselected state, the last GF in the sequence having its controlled terminals connected in series between the capacitor and a source of ground potential to provide a ground-discharge path for the capacitor whenever the last bit assumes the nonselected state, each preceding GF being connected in series between the first controlled terminal of the following LF and a source of ground potential to provide a ground-discharge path for the capacitor whenever the associated bit assumes the nonselected state and all following bits have assumed the selected state.   
     
     
       9. A gate circuit as recited in claim 8, wherein: an additional binary data signal is provided, the state of which is to be detected in combination with the two others, the two possible states of the additional data signal being capable of (1) charging and (2) discharging the capacitor as recited in claim 8, the reverse being true of the complement of the additional data signal; and   the means for supplying the capacitor-charging signal comprises means for connecting a selected one of the additional data signal and its complement to the first controlled terminal of the first LF, the one being selected to charge the capacitor when the additional data signal assumes the selected state, and to provide a ground-discharge path for the capacitor whenever the additional bit assumes the nonselected state and all bits recited in claim 8 have assumed the selected state.   
     
     
       10. A gate circuit as recited in claim 8, wherein: the states of the binary data signals are (1) a discrete potential capable of rendering the FETs conductive and (2) a ground potential not so capable;   the second data input signal in each case comprises the discrete potential when the associated bit assumes the non-selected state to render each GF conductive in that case; and   the source of ground potential to which a controlled terminal of each GF is connected comprises the first data input signal associated with that GF, which is a ground potential whenever that GF is conductive. .Iadd. 11. A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination:   a. a first plurality of solid state switching circuits, each having at least one insulated gate transistor of a first channel type;   b. a second plurality of solid state switching circuits, each having at least one insulated gate transistor of said first channel type; wherein   c. each of said first and second switching circuits have at least one signal input terminal and first and second switch terminals, and wherein   d. said first switching circuits are cascade coupled between said first reference signal means and said system output means such that at least one of said first switch terminals is coupled to said first reference signal, at least one of said second switch terminals is coupled to said system output means, and the remaining of said second switch terminals are connected to at least one of said first switch terminals; and wherein   e. said second plurality of switching circuits are connected such that at least one of said second switch terminals is connected to said second reference signal input means and in common with the remaining of said second switch terminals, and at least one of said first switch terminals is connected to said system output means with others of said first switch terminals being connected to at least one of said first switch terminals of said first switching circuit by means other than one of said first insulated gate transistors; and wherein   f. when a preselected value of said input signal is coupled to said system, said first switching circuits are OPEN and said second switching circuits are CLOSED, thereby coupling said first reference signal to said system output means; and wherein   g. for substantially all other values of said input signal coupled to said system, at least one of said first switching circuits is CLOSED and at least one of said second switching circuits is OPEN, thereby coupling said second reference signal to said system's output means. .Iaddend..Iadd. 12. A digital decoding system in accordance with claim 11 wherein said first channel type is P-channel. .Iaddend..Iadd. 13. A digital decoding system in accordance with claim 11 wherein said first channel type is N-channel. .Iaddend..Iadd. 14. A digital decoding system in accordance with claim 11 wherein said first and second switching circuits are formed within a common semiconductor substrate, and selectively interconnected by selectively doped regions within said common semiconductor substrate. .Iaddend..Iadd. 15. A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination:   a. a first plurality of insulated gate field-effect transistors of a first channel type, each having source, drain and gate terminals; and   b. a second plurality of insulated gate field-effect transistors of said first channel type, each having source, drain and gate terminals; wherein   c. said first plurality of insulated gate field-effect transistors are source-to-drain cascade connected with the drain terminal of the first insulated gate field-effect transistor in the cascade being connected to said first reference signal means and the source terminal of the last insulated gate field-effect transistor in the cascade being connected to said system output means; and wherein   d. said second plurality of insulated gate field-effect transistors are connected such that the source terminal of each of said second plurality of transistors is connected in common to said second reference signal means with at least one of the drain terminals of said second plurality of transistors being connected to said systems output means with other drain terminals connected by means other than one of said first insulated gate field-effect transistors to a respective source terminal of a transistor of said first plurality of transistors; and wherein   e. when a predetermined value of said digital input signal is coupled to the gate of said first and second pluralities of transistors, said reference signal is coupled to said system output means; responsive to a second predetermined value of said input signal said second reference signal is coupled to said output means through one of said second plurality of transistors and the source-drain path of at least one of said first plurality of transistors, and responsive to a third predetermined value of said input said second reference signal is coupled to said output means only through one of said second plurality of transistors. .Iaddend..Iadd. 16. A digital decoding system in accordance with claim 15 wherein said first channel type is P-channel. .Iaddend..Iadd. 17. A digital decoding system in accordance with claim 15 wherein said first channel type is N-channel. .Iaddend..Iadd. 18. A digital decoding system in accordance with claim 15 wherein said first and second switching circuits are formed within a common semiconductor substrate, and selectively interconnected by selectively doped regions within said common semiconductor substrate. .Iaddend.