Triple-slope analog-to-digital converters

Abstract

A ramp type analogue to digital converter including an integrating circuit the output of which is first set to a level dependent upon the magnitude of an analogue input voltage to be converted. A reference signal is then applied to ramp down the integrator output level to a datum level and the conversion is effected by counting clock pulses while the integrator output is ramping down to datum level. The magnitude of the reference signal and the numerical weighting of the clock pulses being counted are scaled down by a common factor when the ramp reaches a value close to the datum level so that the slope of the ram is reduced and the resolution of conversion is increased as it approaches datum. Thus, compared with a ramp type digital voltmeter having a constant slope discharge ramp and a given resolution, the discharge time is reduced for the same resolution of conversions.

I claim: 
     
       1. An analog-to-digital converter comprising an integrating means having an input and an output, means for applying an analog input signal to be converted to the input of the integrating means to drive the integrating means output from a datum level to a level dependent upon the magnitude of the input signal, a source of a reference signal, means for applying the reference signal to the input of the integrating means to drive the integrating means output to the datum level and thereby generate a ramp function, a counter, means for generating clock pulses, means for causing clock pulses to be counted by the counter during an interval commencing with the application of the reference signal, means for applying a first increment to the ramp function before the ramp reaches the datum level a first time, means for detecting when the ramp reaches the datum level, means for applying to the ramp function a second increment equal in magnitude but opposite in polarity to said first increment, and means for scaling down the reference signal and the numerical weighting with which the clock pulses are counted by a common factor, the means for applying the second increment and the means for scaling down the reference signal and the numerical weighting of the clock pulses being responsive to operation of said detecting means when the ramp reaches the datum level said first time, and said detecting means being operative to determine the count in the counter when the ramp reaches the datum level a second time, whereby the count in the counter when the ramp reaches the datum level said second time provides a digital representation of the analog signal magnitude. 
     
     
       2. A converter according to claim 1, wherein said first increment drives the integrating means output towards the datum .[.leve.]. .Iadd.level.Iaddend., and wherein said scaled-down reference signal is of the same polarity as the first mentioned reference signal and the clock pulses of reduced numerical weighting are counted additively. 
     
     
       3. A counter according to claim 1, wherein said first increment is applied to said ramp at substantially the commencement of the application of the reference signal. 
     
     
       4. A converter according to claim 1, wherein there is further provided means coupled to said counter for decoding and displaying the digital representation of the analog signal magnitude, and wherein said integrating means is a substantially linear integrator and a predetermined number of clock pulses are counted by said counter as the integrator output is driven from said datum level to said level dependent on said input signal.