Semiconductor devices

Abstract

A method for making an IGFET is described. The method utilizes impurity ion implantation into the surface channel to determine the conductivity thereof. The advantages include special impurity profiles providing improved performance, better control over important parameters such as threshold voltage, the manufacture of improved tetrodes, and the manufacture of improved ICs using for example N- and P-channel devices, and depletion and enhancement devices combined in a single chip.

What is claimed is: 
     
       1. A method of manufacturing at least one insulated gate field effect transistor, comprising forming in a semiconductor body portion of one conductivity type adjacent a surface thereof by introducing opposite-type forming impurities therein spaced first and second low resistivity regions of the opposite conductivity type to constitute at least part of source and drain electrodes of the transistor, implanting ions of an impurity element in a third surface.Iadd.-adjacent .Iaddend.region of the body portion extending between the first and second regions .[.to determine the conductivity thereof.]. to form at least a portion of a .[.current-carrying.]. channel .Iadd.region located in the third region and whose conductivity is determined by the implanted ions and which functions to carry current .Iaddend.between the source and drain electrodes .Iadd.when appropriate potentials are applied to the transistor, .Iaddend.providing a gate electrode on an insulating layer on said surface and extending over at least said portion of the channel .Iadd.region, .Iaddend.and making electrical connections to the low resistivity source and drain electrodes, and to the gate electrode. 
     
     
       2. A method as set forth in claim 1 wherein the implanted ions are of the one-type conductivity and form a channel .[.portion.]. .Iadd.region .Iaddend.of the one-type conductivity having a resistivity which is lower than that of the immediately underlying part of the said semiconductor body portion whereby said transistor is capable of operation in the enhancement mode. 
     
     
       3. A method as set forth in claim 2 wherein the first and second low resistivity regions are formed by diffusion prior to the ion-implantation step. 
     
     
       4. A method as set forth in claim 2 wherein the said semiconductor body portion of one conductivity type is provided as a layer on a substrate of the one conductivity type and of lower resistivity. 
     
     
       5. A method as set forth in claim 1 wherein the insulating layer comprises silicon oxide, and phosphorous ions are implanted in the silicon oxide insulating layer to stabilize same. 
     
     
       6. A method of manufacturing at least one insulated gate field effect tetrode transistor, comprising forming in a semiconductor body portion of one conductivity type adjacent a surface thereof by introducing opposite-type forming impurities therein spaced first, second and third low resistivity regions of the opposite conductivity type to constitute at least part of the source and drain electrodes of the transistor and defining between the first and second regions a first .[.current-carrying.]. channel .Iadd.region .Iaddend.and between the second and third regions a second .[.current-carrying.]. channel .Iadd.region, .Iaddend.implanting ions of an impurity element of the opposite conductivity type in the surface region of the body portion constituting at least the first channel region to determine the conductivity thereof, .Iadd.said channel regions carrying current between the source and drain regions when appropriate potentials are applied to the transistor, .Iaddend.providing a first gate electrode on an insulating layer on said surface and extending over at least part of the first channel .Iadd.region .Iaddend.and providing a second gate electrode on an insulating layer on said surface and extending over at least part of the second channel .Iadd.region, .Iaddend.and making electrical connections to the first and third low resistivity regions, and to the gate electrodes. 
     
     
       7. A method as set forth in claim 6 wherein ions of the opposite conductivity type are implanted also in the second channel region. 
     
     
       8. A method as set forth in claim 7 wherein ions of the one conductivity type are implanted over only a portion of at least one of the channel regions and adjacent its source electrode. 
     
     
       9. A method of manufacturing a .[.semiconductOr.]. .Iadd.semiconductor .Iaddend.device comprising at least a first insulated gate field effect transistor and at least a second .[.other.]. circuit element, comprising forming in a first part of a semiconductor body portion adjacent a surface thereof said .[.other.]. .Iadd.second .Iaddend.circuit element, forming in a second part .[.of the semiconductor body portion.]. of one conductivity type .Iadd.of the semiconductor body portion .Iaddend.adjacent a surface thereof by introducing opposite-type forming impurities therein spaced first and second low resistivity regions of the opposite conductivity type to constitute at least part of source and drain electrodes of the field effect transistor, implanting ions of an impurity element in a third surface.Iadd.-adjacent .Iaddend.region of the body portion extending between the first and second regions .[.to determine the conductivity thereof.]. to form at least a portion of a .[.current carrying.]. channel .Iadd.region located in the third region and whose conductivity is determined by the implanted ions and which functions to carry current .Iaddend.between the source and drain electrodes .Iadd.when appropriate potentials are applied to the transistor.Iaddend., providing a gate electrode on an insulating layer on said surface and extending over at least said portion of the channel .Iadd.region.Iaddend., and making electrical connections to the low resistivity source and drain electrodes, to the gate electrode, and to the .[.other.]. .Iadd.second .Iaddend.circuit element. 
     
     
       10. A method as set forth in claim 9 wherein the .[.other.]. .Iadd.second .Iaddend.circuit element .[.is also an.]. .Iadd.constitutes a second .Iaddend.insulated gate field effect transistor having different properties than the first transistor determined by the ion implantation step. .[.11. A method as set forth in claim 10 wherein the ion implantation step employs ions of said one conductivity type and establishes an island of said one conductivity type in a substrate of said opposite conductivity type and constituting said second part of the 
     
     
        semiconductor body portion..]. 12. A method as set forth in claim 10 wherein the first and second insulated gate field effect transistors comprise channels of opposite conductivity types .Iadd.which are located at least partly in regions whose conductivity is .Iaddend.determined by 
     
     
        ion implantation. 13. A method as set forth in claim 10 wherein the first and second insulated gate field effect transistors comprise channels of the same conductivity type but said transistors are adapted to operate in different ones of the depletion and enhancement modes. .[.14. A method as claimed in claim 9 wherein the ion-implantation step comprises implanting in a region of the second semiconductor body portion of one conductivity type a concentration of ions of an impurity element characteristic of the opposite conductivity type, said implanted ion concentration determining a region of the opposite conductivity type which extends to one surface of the body portion and is surrounded within the body portion by a region of the one conductivity type, and forming the first insulated gate field effect transistor in the implanted region of the opposite conductivity type, and at least the other circuit element in another region of the one conductivity type..]. .Iadd. 15. A method as set forth in claim 1 wherein ions of the opposite type conductivity are implanted into the channel region to adjust the threshold voltage of the transistor. .Iaddend..Iadd. 16. In a method of manufacturing a semiconductor device comprising at least one insulated gate field effect device, comprising forming in a semiconductor body portion of one-type conductivity adjacent a surface thereof by introducing opposite-type forming impurities therein spaced first and second low resistivity regions of the opposite-type conductivity to constitute at least part of source and drain regions of the device, said source and drain regions defining between them a device channel region adjacent said surface, providing a gate electrode on an insulating layer on said surface and extending over said channel region, and making electrical connections to the low resistivity source and drain regions and to the gate electrode whereby when operating potentials are applied the device exhibits a threshold voltage which when applied to the gate causes current conduction in the channel region between the source and drain regions, the improvement comprising implanting ions of an impurity element in at least a portion of the channel region under such conditions that substantially all of said implanted ions are confined to the channel region and in such number that the threshold voltage is accurately and reproducibly controlled by the implanted ions. .Iaddend. .Iadd. 17. The method of claim 16 wherein the implantation step follows provision of the source and drain regions and provision of the insulating layer. .Iaddend..Iadd. 18. The method of claim 16 wherein plural insulated gate field effect transistors are made in a common semiconductor body, ions being implanted into at least several of the transistor channel regions to control their threshold voltage. .Iaddend..Iadd. 19. The method of claim 18 wherein at least one of the transistors is of the enhancement type, and at least one is of the depletion type. .Iaddend..Iadd. 20. The method of claim 16 wherein prior to the ion implantation step to control the threshold voltage, ions are implanted into the surface of the body to form a surface region of one type conductivity that is of lower resistivity than that of underlying one type body portions. .Iaddend..Iadd. 21. The method of claim 16 wherein the body is of P-type material, the channel is N-type, and acceptor ions are implanted in the channel region to accurately determine the threshold voltage. .Iaddend..Iadd. 22. In a method of manufacturing a semiconductor device comprising at least one insulated gate field effect transistor, comprising forming in a semiconductor body portion of one-type conductivity adjacent a surface thereof by introducing opposite-type forming impurities therein spaced first and second low resistivity regions of the opposite-type conductivity to constitute at least part of source and drain regions of the transistor, said source and drain regions defining between them a transistor channel region adjacent said surface, providing a gate electrode on an insulating layer on said surface and extending over said channel region, and making electrical connections to the low resistivity source and drain regions and to the gate electrode whereby when operating potentials are applied to the transistor current conduction occurs in the channel region between the source and drain regions, the improvement comprising implanting ions of an impurity element in at least a portion of the channel region in such number as to determine the doping concentration of said channel portion. .Iaddend..Iadd. 23. The method of claim 22 wherein one-type forming impurity ions are implanted into the whole surface of the body portion including parts extending outside the source and drain regions, and opposite-type forming impurity ions are implanted into the channel region.