USH1883HExpiredUtility

Continuous-time adaptive learning circuit

Assignee: US NAVYPriority: Dec 3, 1992Filed: Dec 3, 1992Granted: Oct 3, 2000
Est. expiryDec 3, 2012(expired)· nominal 20-yr term from priority
H03H 21/0001H03H 21/0012
27
PatentIndex Score
0
Cited by
10
References
8
Claims

Abstract

A continuous-time multiplier-integrator-multiplier circuit in which the integrator is a transconductance-C circuit. This permits the integrators to have long time constants despite being tightly fabricated on an integrated semiconductor chip. The multipliers can preferably be Gilbert multipliers, to improve circuit frequency response.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A multiplier-integrator-multiplier circuit, comprising: means for receiving a first and a second input signal;   first multiplier means for producing a first intermediate signal proportional to the product of said first and said second input signals;   integrator means for producing a second intermediate signal proportional to the integral of said first output signal;   second multiplier means for producing a third intermediate signal proportional to the product of said second signal and a third input signal;   wherein said integrator means is a transconductance-C circuit.   
     
     
       2. The circuit of claim 1, wherein said first multiplier, transconductance-C circuit, and said second multiplier circuit are in the form of a semiconductor monolith. 
     
     
       3. The circuit of claim 2, wherein the transistors of said first multiplier, transconductance-C circuit, and said second multiplier circuit are FET's. 
     
     
       4. The circuit of claim 2, wherein the transistors of said first multiplier, transconductance-C circuit, and said second multiplier circuit are bipolar transistors. 
     
     
       5. The circuit of claim 2, wherein the transistors of said first multiplier, transconductance-C circuit, and said second multiplier circuit are a combination of FET's and bipolar transistors. 
     
     
       6. The circuit of claim 1, wherein said first and said second multiplier means are each a four quadrant Gilbert multiplier circuit. 
     
     
       7. The circuit of claim 5, wherein said first and said second multiplier means are each a four quadrant Gilbert multiplier circuit. 
     
     
       8. (New) A multiplier-integrator-multiplier circuit, comprising: means for receiving a first and second input signal;   first multiplier means for producing a first intermediate signal proportional to the product of said first and said second input signals;   integrator means for producing a second intermediate signal proportional to the integral of said first intermediate signal;   second multiplier means for producing a third intermediate signal proportional to the product of said second intermediate signal and a third input signal;   wherein said circuit further comprises means for causing said first and said third input signals to be substantially the same; and   wherein said integrator means is a transconductance-C circuit.

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