Method and apparatus for pattern sensitivity stress testing of memory systems

Abstract

A method and apparatus for stress testing a computer memory system is disclosed. A sequential series of bit patterns, comprising 1's and 0's, is impressedd upon a computer memory so that, during testing, every memory cell stores a 1 while the eight adjacent neighboring memory cell stores 0's. Subsequently, the complimentary bit patterns are impressed upon memory, wherein every memory cell, at some time during the test, stores a 0 while the eight immediately adjacent neighboring memory cells store 1's. The disclosed bit pattern maximizes stress on the cells, In an interleaved dual memory bank configuration, memory cells are sequentially accessed from the highest to the lowest address of one memory bank, while memory cells are sequentially accessed from the lowest to the highest memory address in the other memory bank. Toggling successive memory accesses between the dual interleaved memory banks maximizes stress on the address driver components of the computer memory system. Preferably, the dual memory banks are simultaneously tested with complementary bit patterns to also maximize stress on the data bus driver and associated components and to maximize demand on the power supply system.

What is claimed is: 
     
       1. A method for stress testing a memory system having a plurality of memory cells capable of being grouped in a plurality of neighborhoods of nine cells, each neighborhood of nine cells including a center cell and eight cells surrounding the center cell, the method comprising the steps of: (a) writing all of the memory cells within a predetermined address range of the memory system with a first value;   (b) writing a plurality of target cells with a second value which is a complement of the first value, each of the target cells being a center cell of each of a first group of neighborhoods of nine cells within the address range, each of the target cells being surrounded by eight non-target cells;   (c) reading all of the non-target cells within the address range and reporting a failure condition if any non-target cells contain other than the first value; and   (d) reading all of the target cells and reporting a failure condition if any target cells contain other than the second value.   
     
     
       2. The method of claim 1, further comprising the step of repeating the steps (a) to (d) until all of the cells within the address range have been written as target cells of a plurality groups of neighborhoods of nine cells. 
     
     
       3. The method of claim 2, further comprising the step of repeating the steps (a) to (d) with the second value written to all of the plurality of memory cells when the step (a) is performed and the first value written to the plurality of target cells when the step (b) is performed. 
     
     
       4. A system for stress testing a computer memory system having a plurality of memory cells arranged in a matrix pattern, comprising: means for writing to a target cell within a neighborhood of 9 cells;   first means for reading the target cells 8 nearest neighbors, detecting a disturbance in the target cells 8 nearest neighbors and determining if the write to the target cells caused the disturbance;   second means for reading the target cell and determining whether a disturbance occurred in the target cell while the first means for reading read the 8 nearest neighbor cells.   
     
     
       5. A system for stress testing a memory system having a plurality of memory cells capable of being grouped in a plurality of neighborhoods of nine cells, each neighborhood of nine cells including a center cell and eight cells surrounding the center cell, the system comprising: first writing means for writing all of the memory cells within a predetermined address range of the memory system with a first value;   second writing means for writing a plurality of target cells with a second value which is a complement of the first value, each of the target cells being a center cell of each of a first group of neighborhoods of nine cells within the address range, each of the target cells being surrounded by eight non-target cells;   first reading means for reading all of the non-target cells within the address range and reporting a failure condition if any non-target cells contain other than the first value; and   second reading means for reading all of the target cells and reporting a failure condition if any target cells contain other than the second value.   
     
     
       6. The system of claim 5, further comprising means for causing the first and second writing means and the first and second reading means to repeat performing the writing and reading functions, respectively until all of the cells within the address range have been written as target cells of a plurality groups of neighborhoods of nine cells. 
     
     
       7. The system of claim 6, further comprising means for causing the first and second writing means and the first and second reading means to repeat performing the writing and reading functions, respectively with the first writing means writing the second value to all of the plurality of memory cells and the second writing means writing the first value to the plurality of target cells. 
     
     
       8. A computer program product comprising: a computer usuable medium having computer readable code embodied therein for stress testing a memory system having a plurality of memory cells capable of being grouped in a plurality of neighborhoods of nine cells, each neighborhood of nine cells including a center cell and eight cells surrounding the center cell, the computer program product comprising:   computer readable program code devices configured to cause a computer effect performing a first writing function by writing all of the memory cells within a predetermined address range of the memory system with a first value;   computer readable program code devices configured to cause a computer effect performing a second writing function by writing a plurality of target cells with a second value which is a complement of the first value, each of a first group of target cells being a center cell of each of a first group of neighborhoods of nine cells within the address range, each of the target cells being surrounded by eight non-target cells;   computer readable program code devices configured to cause a computer effect performing a first reading function by reading all of the non-target cells within the address range and reporting a failure condition if any non-target cells contain other than the first value; and   computer readable program code devices configured to cause a computer effect performing a second reading function by reading all of the target cells and reporting a failure condition if any target cells contain other than the second value.   
     
     
       9. The computer program product of claim 8, further comprising computer readable program code devices configured to cause a computer to effect repeating performing the first and second writing functions and the first and second reading functions until all of the cells within the address range have been written as target cells of a plurality groups of neighborhoods of nine cells. 
     
     
       10. The computer program product of claim 9, further comprising the computer readable program code devices configured to cause a computer to effect repeating performing the first and second writing functions and the first and second reading functions, with the second value written to all of the plurality of memory cells and the first value written to the plurality of target cells.