Nonvolatile memory system for storing a key word and sensing the presence of an external loader device and encryption circuit

Abstract

A nonvolatile memory system is disclosed which will store a key or digital word for a period of time of approximately three years with minimum power consumption. The nonvolatile memory system includes a nonvolatile static random access memory for receiving and storing a key word from a loader, and a nonvolatile memory sequence control circuit which provides logic signals for controlling read and write operations of the nonvolatile static RAM, as well as logic signals to allow for transfer or down loading of the key word from the loader to the RAM. In addition, the nonvolatile memory sequence control circuit provides logic signals to interface with an encryption device which allows the key word to be transferrred or up loaded from the nonvolatile static RAM to the encryption device and logic signals for storing the key word in a nonvolatile electrically erasable programmable read only memory (PROM) and then bringing the nonvolatile static RAM to a low power standby state. An erasable PROM (EPROM) is used to control the sequencing of operations within the nonvolatile static RAM with addressing for the EPROM being provided by the nonvolatile memory sequence control circuit. The EPROM and the nonvolatile memory sequence control circuit may be also brought to a low power standby state by a power control signal provided by the memory sequence control circuit.

What is claimed is: 
     
       1. A nonvolatile memory system for sensing the presence of an external loader device and then receiving a key word of up to 1024 digital data bits from said external loader device, for storing said key word therein for a period of time of up to three years and then transferring said key word to said encryption circuit, said nonvolatile memory system comprising: erasable programmable read-only memory means for providing a plurality of program instructions, each of said program instructions being provided by said erasable programmable read-only memory means in response to a binary address supplied to said erasable programmable read-only memory means, said program instructions controlling a sequencing of operations within said nonvolatile memory system, each of said program instructions having at least eight digital data bits;   nonvolatile static digital data storage means for receiving said key word from said encryption circuit and storing said key word therein, said nonvolatile static digital data storage means having first and second data input/outputs, a write enable input and a nonvolatile enable input;   first address generating means for supplying each binary address to said erasable programmable read-only memory means;   second address generating means for supplying sequential binary addresses to said nonvolatile static digital data storage means, each sequential binary address supplied to said nonvolatile static digital data storage means selectively allowing said nonvolatile static digital data storage means to store therein two digital data bits of said key word from said external loader device or allowing two digital data bits of said key word to be retrieved from said nonvolatile static digital data storage means for transfer to said encryption circuit;   clock generating means for providing a system clock signal;   counter means for generating PHI0, PHI1, PHI2, PHI3 and PHI012 clock signals in response to the system clock signal being provided to said counter means by said clock generating means and for providing a first reset signal;   said first address generating means being incremented by the PHI012 clock signal generated by said counter means and being reset by the first reset signal provided by said counter means;   first, second, and third program instruction storage means for latching therein said plurality of program instructions provided by said erasable programmable read-only memory means, each of said program instructions being latched into said first, second and third program instruction storage means respectively by said PHI0, PHI1 and PHI2 clock signals;   said first program instruction storage means providing a power down signal, said power down signal setting said nonvolatile static digital data storage means at a power down standby state to allow for retention of said key word within said nonvolatile static digital data storage means for said period of time of up to three years;   multiplexer means for sensing the presence of said external loader device and if said external loader device is not present testing for the presence of said encryption circuit, said multiplexer means providing a first digital logic signal indicating the presence of said external loader device or the presence of said encryption circuit, said multiplexer means being enabled to sense for the presence of said external loader device by one of the plurality of program instructions latched within said first program instruction storage means and being selectively enabled to sense for the presence of said encryption circuit by another of the plurality of program instructions latched within said first program instruction storage means;   control circuit means for providing a parallel load signal to said first address generating means in response to the first digital logic signal provided by said multiplexer means, said parallel load signal effecting the parallel loading of the program instruction latched within said second program instruction storage means into said first address generating means, one of said plurality of program instructions when parallel loaded into said first address generating means initiating the transfer of the key word from said external loader device to said nonvolatile static digital data storage means and another of said plurality of program instructions when parallel loaded into said first address generating means initiating the transfer of the key word from said nonvolatile static digital data storage means to said encryption circuit;   said control circuit means providing a second reset signal for resetting said second address generating means and an increment second address generating means clock signal for incrementing said second address generating means so that said second address generating means provides said sequential binary addresses to said nonvolatile static digital data storage means;   said control circuit means providing a read/write digital logic signal to said nonvolatile static digital data storage means for controlling storage of said key word in said nonvolatile static digital data storage means and retrieval of said key word from said nonvolatile static digital data storage means;   demultiplexer means for effecting the transfer of said key word from said external loader device to said nonvolatile static digital data storage means, said demultiplexer means being enabled to effect the transfer of said key word from said external loader device to said nonvolatile static digital data storage means by one of the plurality of program instructions latched within said first program instruction storage means;   flip-flop means for effecting the transfer of said key word from said nonvolatile static digital data storage means to said encryption circuit; and   said control circuit means providing an increment flip-flop means clock signal to effect the transfer of said key word from said nonvolatile static digital data storage means to said encryption circuit.   
     
     
       2. The nonvolatile memory system of claim 1 further comprising power control circuit means for generating an enable signal for enabling said erasable programmable read-only memory means, a third reset signal for resetting said counter means and a power up signal, said power up signal and said enable signal from said power control circuit means setting said nonvolatile static digital data storage means to a power up state to selectively allow for the storage of said key word within said nonvolatile static digital data storage means and the retrieval of said key word from said nonvolatile static digital data storage means. 
     
     
       3. The nonvolatile memory system of claim 2 wherein said power control circuit means comprises: first and second D flip-flops, each of said first and second flip-flops having a data input, a clock input, a Q output, a not Q output, a preset input and a reset input;   the clock inputs of said first and second flip-flops receiving said system clock signal, the preset inputs of said first and second flip-flops being connected to a logic one signal;   a voltage sensing circuit having an output connected to the clear input of said first flip-flop and the clear input of said second flip-flop;   a first NAND gate having a first input connected to the not Q output of said first flip-flop, a second input connected to the not Q output of said second flip-flop, and an output connected to the data input of said first flip-flop;   a second NAND gate having a first input connected to the Q output of said first flip-flop, a second input connected to the Q output of said second flip-flop and an output;   a first inverter having an input for receiving said power down signal and an output;   a third NAND gate having a first input connected to the Q output of said first flip-flop, a second input connected to the output of said inverter and an output;   a fourth NAND gate having a first input connected to the output of said first NAND gate, a second input conneced to the output of said second NAND gate, a third input connected to the output of said third NAND gate and an output connected to the data input of said second flip-flop;   a fifth NAND gate having a first input for receiving said power down signal, a second input connected to the not Q output of said second flip-flop and an output;   a sixth NAND gate having a first input connected to the output of said fifth NAND gate, a second input connected to the Q output of said first flip-flop, a third input connected to said logic one signal and an output;   a seventh NAND gate having a first input connected to said logic one signal, a second input connected to the output of said sixth NAND gate, a third input connected to the output of said voltage sensing circuit and an output for providing said enable signal; and   a second inverter having an input connected to the output of said seventh nand gate and an output for providing said third reset signal.   
     
     
       4. The nonvolatile memory system of claim 1 further comprising a nonvolatile static RAM interface circuit means, said nonvolatile static RAM interface circuit means serially recieing pairs of digital data bits of said key word, temporarily storing a first bit of each pair of digital data bits of said key word and then for each pair providing simultaneously the first and second digital data bits respectively to the first and second data input/outputs of said nonvolatile static digital data storage means. 
     
     
       5. The nonvolatile memory system of claim 4 wherein said nonvolatile static RAM interface circuit means comprises: first and second D flip-flops, each of said first and second flip-flops having a data input, a clock input, a Q output, and a clear input;   the clear and preset inputs of said first flip-flop and the clear input of said second flip-flop being connected to a logic one signal;   the clock input of said second flip-flop receiving said PHI3 clock signal;   the data input of said first flip-flop receiving the first bit of each pair of digital data bits of said key word;   the Q output of said second flip-flop connected to the nonvolatile enable input of said nonvolatile static digital data storage means;   a first NOR gate having a first input for receiving said read/write digital logic signal, a second input for receiving address bit zero from said second address generating means and an output connected to the clock input of said first flip-flop;   a first inverter having an input for receiving address bit zero from said second address generating means and an output;   a second NOR gate having a first input connected to the output of said first inverter, a second input for receiving said read/write digital logic signal and an output;   a third NOR gate having a first input connected to the Q output of said second flip-flop, a second input connected to ground and an output;   a fourth NOR gate having a first input connected to the output of said second NOR gate, a second input connected to the output of said third NOR gate and an output connected to the write enable input of said nonvolatile static digital data storage means;   a second inverter having an input connected to the output of said fourth NOR gate and an output connected to output enable input of said nonvolatile static digital data storage means;   a first tristate output buffer gate having a data input connected to the Q output of said first flip-flop, an enable input connected to the output of said fourth NOR gate and an output connected to the first data input/output of said nonvolatile digital data storage means;   a second tristate output buffer gate having a data input for receiving each digital data bit of said key word, an enable input connected to the output of said fourth NOR gate and an output connected to the second data input/output of said nonvolatile static digital data storage means;   a third tristate output buffer gate having an input connected to the first data input/output of said nonvolatile digital data storage means, an enable input for receiving address bit zero from said second address generating means and an output; and   a fourth tristate output buffer gate having an input connected to the second data input/output of said nonvolatile static digital data storage means, an enable input connected to the output of said first inverter and an output connected to the output of said third tristate buffer.   
     
     
       6. The nonvolatile memory system of claim 1 wherein said counter means comprises: a first inverter having an input for receiving said third reset signal and an output;   a first D flip-flop having a data input connected to a logic one signal, a clock input for receiving said system clock signal, a clear input connected to the output of said first inverter and a not Q output;   a second D flip-flop having a data input, a clock input for receiving said system clock signal, a clear input connected to the not Q output of said first flip-flop, a not Q output connected to the data input of said second D flip-flop and a Q output;   a third D flip-flop having a data input, a clock input connected to the Q output of said second flip-flop, a clear input connected to the not Q output of said first flip-flop, a not Q output connected to the data input of said third D flip-flop and a Q output;   a second inverter having an input connected to the not Q output of said first flip-flop and an output for providing said first reset signal;   a first NOR gate having a first input for receiving said system clock signal, a second input connected to the not Q output of said first flip-flop, a third input connected to the Q output of said second flip-flop, a fourth input connected to the Q output of said third flip-flop and an output for providing said PHI0 clock signal;   a second NOR gate having a first input for receiving said system clock signal, a second input connected to the not Q output of said second flip-flop, a third input connected to the not Q output of said third flip-flop and an output for providing said PHI1 clock signal;   a third NOR gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop, a third input connected to the not Q output of said third flip-flop and an output for providing said PHI2 clock signal;   a fourth NOR gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop, a third input connected to the Q output of said third flip-flop and an output for providing said PHI3 clock signal;   a fifth NOR gate having a first input connected to the not Q output of said first flip-flop, a second input for receiving said system clock signal, a third input and an output for providing said PHI012 clock signal;   a NAND gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop and an output; and   a third inverter having an input connected to the output of said NAND gate and an output connected to the third input of said fifth NOR gate.   
     
     
       7. The nonvolatile memory system of claim 1 wherein said first address generating means comprises: first through tenth negative edge triggered J K flip-flops, each of said J K flip-flops having a J input connected to a logic one signal, a K input connected to said logic one signal, a clock input, a preset input, a clear input and a Q output;   the clock input of said first J K flip-flop receiving said PHI012 clock signal;   the Q output of said first J K flip-flop being connected to the clock input of said second J K flip-flop, the Q output of said second J K flip-flop being connected to the clock input of said third J K flip-flop, the Q output of said third J K flip-flop being connected to the clock input of said fourth J K flip-flop, the Q output of said fourth J K flip-flop being connected to the clock input of said fifth J K flip-flop, the Q output of said fifth J K flip-flop being connected to the clock input of said sixth J K flip-flop, the Q output of said sixth J K flip-flop being connected to the clock input of said seventh J K flip-flop, the Q output of said seventh J K flip-flop being connected to the clock input of said eighth J K flip-flop, the Q output of said eighth J K flip-flop being connected to the clock input of said ninth J K flip-flop and the Q output of said ninth J K flip-flop being connected to the clock input of said tenth J K flip-flop;   first through tenth load circuits, each of said load circuits having a data input, a reset input for receiving said first reset signal, a load input for receiving said parallel load signal, a data input, a preset output and a clear output;   the data inputs of said first and second load circuits being connected to a logic zero and the data inputs of said third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to first, second, third, fourth, fifth, sixth, seventh and eighth Q outputs of said second program instruction storage means;   the preset outputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the preset inputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth J K flip-flops; and   the clear outputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the clear inputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth J K flip-flops.   
     
     
       8. The nonvolatile memory system of claim 7 wherein each of said load circuits comprises: a first NAND gate having a first input for receiving said first reset signal, a second input and an output;   a second NAND gate having a first input for receiving said first reset signal, a second input and an output;   an inverter having an input for receiving said parallel load signal and an output connected to the second input of said second nand gate;   a third NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said second NAND gate and an output connected to the clear input of a respective one of said J K flip-flops; and   a fourth NAND gate having a first input for receiving said parallel load signal, an output connected to the preset input of a respective one of said J K flip-flops and a second input;   the second inputs of the first and fourth NAND gates of said first and second load circuits being connected to said logic zero signal and the second inputs of the first and fourth NAND gates of said third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the first, second, third fourth, fifth, sixth, seventh and eighth Q outputs of said second program instruction storage means.   
     
     
       9. The nonvolatile memory system of claim 1 wherein each of said first, second and third program instruction storage means comprises eight negative edge triggered D flip-flops. 
     
     
       10. The nonvolatile memory system of claim 1 wherein said second address generating means comprises: first through eleventh negative edge triggered J K flip-flops, each of said J K flip-flops having a J input connected to a logic one signal, a K input connected to said logic one signal, a preset input connected to said logic one signal, a clock input, a clear input and a Q output;   the clock input of said first J K flip-flop receiving said increment second address generating means clock signal;   the clear input of each of said J K flip-flops receiving said second reset signal;   the Q output of said first J K flip-flop being connected to the clock input of said second J K flip-flop, the Q output of said second J K flip-flop being connected to the clock input of said third J K flip-flop, the Q output of said third J K flip-flop being connected to the clock input of said fourth J K flip-flop, the Q output of said fourth J K flip-flop being connected to the clock input of said fifth J K flip-flop, the Q output of said fifth J K flip-flop being connected to the clock input of said sixth J K flip-flop, the Q output of said sixth J K flip-flop being connected to the clock input of said seventh J K flip-flop, the Q output of said seventh J K flip-flop being connected to the clock input of said eighth J K flip-flop, the Q output of said eighth J K flip-flop being connected to the clock input of said ninth J K flip-flop, the Q output of said ninth J K flip-flop being connected to the clock input of said tenth J K flip-flop and the Q output of said tenth J K flip-flop being connected to the clock input of said eleventh J K flip-flop.   
     
     
       11. The nonvolatile memory system of claim 1 wherein said flip-flop means comprises a negative edge triggered D type flip-flop. 
     
     
       12. The nonvolatile memory system of claim 1 wherein at least one of the program instructions latched within said third program instruction storage means when supplied to and decoded by said control circuit means will result in said control circuit means providing said read/write digital logic signal to said nonvolatile static digital data storage means. 
     
     
       13. A nonvolatile memory system for sensing the presence of an external loader device and then receiving a key word of up to 1024 digital data bits from said external loader device, for storing said key word therein for a period of time of up to three years and for sensing a presence of an encryption circuit and then transferring said key word to said encryption circuit, said nonvolatile memory system comprising: erasable programmable read-only memory means for providing a plurality of program instructions, each of said program instructions being provided by said erasable programmable read-only memory in response to a binary address supplied to said erasable programmable read-only memory means, said program instructions controlling a sequencing of operations within said nonvolatile memory system, each of said program instructions having at least eight digital data bits;   nonvolatile static digital data storage means for receiving said key word from said encryption circuit and storing said key word therein, said nonvolatile static digital data storage means having first and second data input/outputs, a write enable input and a nonvolatile enable input;   first address generating means for supplying each binary address to said erasable programmable read-only memory means;   second address generating means for supplying 512 sequential binary addresses to said nonvolatile static digital data storage means, each sequential binary address supplied to said nonvolatile static digital data storage means selectively allowing said nonvolatile static digital data storage means to store therein two digital data bits of said key word from said external loader device or allowing two digital data bits of said key word to be retrieved from said nonvolatile static digital data storage means for transfer to said encryption circuit;   clock generating means for providing a system clock signal;   counter means for generating PHI0, PHI1, PHI2, PHI3 and PHI012 clock signals in response to the system clock signal being provided to said counter means by said clock generating means and for providing a first reset signal;   said first address generating means being incremented by the PHI012 clock signal generated by said counter means and being reset by the first reset signal provided by said counter means;   first, second, and third program instruction storage means for latching therein said plurality of program instructions provided by said erasable programmable read-only memory means, each of said program instructions being latched into said first, second and third program instruction storage means respectively by said PHI0, PHI1 and PHI2 clock signals;   said first program instruction storage means providing a power down signal, said power down signal setting said nonvolatile static digital data storage means at a power down standby state to allow for retention of said key word within said nonvolatile static digital data storage means for said period of time of up to three years;   multiplexer means for sensing the presence of said external loader device and if said loader device is not present testing for the presence of said encryption circuit, said multiplexer means providing a first digital logic signal indicating the presence of said external loader device or the presence of said encryption circuit, said multiplexer means being enabled to sense for the presence of said external loader device by one of the plurality of program instructions latched within said first program instruction storage means and being selectively enabled to sense for the presence of said encryption circuit by another of the plurality of program instructions latched within said first program instruction storage means;   control circuit means for providing a parallel load signal to said first address generating means in response to the first digital logic signal provided by said multiplexer means, said parallel load signal effecting the parallel loading of the program instruction latched within said second program instruction storage means into said first address generating means, one of said plurality of program instructions when parallel loaded into said first address generating means initiating the transfer of the key word from said external loader device to said nonvolatile static digital data storage means and another of said plurality of program instructions when parallel loaded into said first address generating means initiating the transfer of the key word from said nonvolatile static digital device storage means to said encryption circuit;   said control circuit means providing a second reset signal for resetting said second address generating means and an increment second address generating means clock signal for incrementing said second address generating means so that said second address generating means provides said 512 sequential binary addresses to said nonvolatile static digital data storage means;   said control circuit means providing a read/write digital logic signal to said nonvolatile static digital data storage means for controlling storage of said key word in said nonvolatile static digital data storage means and retrieval of said key word from said nonvolatile static digital data storage means;   demultiplexing means for effecting the transfer of said key word from said external loader device to said nonvolatile static digital data storage means, said demultiplexer means being enabled to effect the transfer of said key word from said external loader device to said nonvolatile static digital data storage means by one of the plurality of program instructions latched within said first program instruction storage means;   flip-flop means for effecting the transfer of said key word from said nonvolatile static digital data storage means to said encryption circuit;   said control circuit means providing an increment flip-flop means clock signal to effect the transfer of said key word from said nonvolatile static digital data storage means to said encryption circuit   power control circuit means for generating an enable signal for enabling said erasable programmable read-only memory means, a third reset signal for resetting said counter means and a power up signal, said power up signal and said enable signal from said power control circuit means setting said nonvolatile static digital data storage means to a power up state to selectively allow for the storage of said key word within said nonvolatile static digital data storage means and the retrieval of said key word from said nonvolatile static digital data storage means; and   nonvolatile static RAM interface circuit means, said nonvolatile static RAM interface circuit means serially receiving pairs of digital data bits of said key word, temporarily storing a first bit of each pair of digital data bits of said key word and then for each pair providing simultaneously the first and second digital data bits respectively to the first and second data input/outputs of said nonvolatile static digital data storage means.   
     
     
       14. The nonvolatile memory system of claim 13 wherein said power control circuit means comprises: first and second D flip-flops, each of said first and second flip-flops having a data input, a clock input, a Q output, a not Q output, a preset input and a reset input;   the clock inputs of said first and second flip-flops receiving said system clock signal, the preset inputs of said first and second flip-flops being connected to a logic one signal;   a voltage sensing circuit having an output connected to the clear input of said first flip-flop and the clear input of said second flip-flop;   a first NAND gate having a first input connected to the not Q output of said first flip-flop, a second input connected to the not Q output of said second flip-flop, and an output connected to data input of said first flip-flop;   a second NAND gate having a first input connected to the Q output of said first flip-flop, a second input connected to the Q output of said second flip-flop and an output;   a first inverter having an input for receiving said power down signal and an output;   a third NAND gate having a first input connected to the Q output of said first flip-flop, a second input connected to the output of said inverter and an output;   a fourth NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said second NAND gate, a third input connected to the output of said third NAND gate and an output connected to the data input of said second flip-flop;   a fifth NAND gate having a first input for receiving said power down signal, a second input connected to the not Q output of said second flip-flop and an output;   a sixth NAND gate having a first input connected to the output of said fifth NAND gate, a second input connected to the Q output of said first flip-flop, a third input connected to said logic one signal and an output;   a seventh NAND gate having a first input connected to said logic one signal, a second input connected to the output of said sixth NAND gate, a third input connected to the output of said voltage sensing circuit and an output for providing said enable signal; and   a second inverter having an input connected to the output of said seventh nand gate and an output for providing said third reset signal.   
     
     
       15. The nonvolatile memory system of claim 13 wherein said nonvolatile static RAM interface circuit means comprises: first and second flip-flops, each of said first and second flip-flops having a data input, a clock input, a Q output, a preset input and a clear input;   the clear and preset inputs of said first flip-flop and the clear input of said second flip-flop being connected to a logic one signal;   the preset input of said second flip-flop receiving said power up signal;   the clock input of said second flip-flop said PHI3 clock signal;   the data input of said first flip-flop being receiving the first bit of each pair of digital data bits of said key word;   the Q output of said second flip-flop connected to the nonvolatile enable input of said nonvolatile static digital data storage means;   a first NOR gate having a first input for receiving said read/write digital logic signal, a second input for receiving address bit zero from said second address generating means and an output connected to the clock input of said first flip-flop;   a first inverter having an input for receiving address bit zero from said second address generating means and an output;   a second NOR gate having a first input connected to the output of said first inverter, a second input for receiving said read/write digital logic signal and an output;   a third NOR gate having a first input connected to the Q output of said second flip-flop, a second input connected to ground and an output;   a fourth NOR gate having a first input connected to the output of said second NOR gate, a second input connected to the output of said third NOR gate and an output connected to the write enable input of said nonvolatile static digital data storage means;   a second inverter having an input connected to the output of said fourth NOR gate and an output connected to output enable input of said nonvolatile static digital data storage means;   a first tristate output buffer gate having a data input connected to the Q output of said first flip-flop, an enable input connected to the output of said fourth NOR gate and an output connected to the first data input/output of said nonvolatile digital data storage means;   a second tristate output buffer gate having a data input for receiving each digital data bit of said key word, an enable input connected to the output of said fourth NOR gate and an output connected to the second data input/output of said nonvolatile static digital data storage means;   a third tristate output buffer gate having an input connected to the first data input/output of said nonvolatile digital data storage means, an enable input for receiving address bit zero from said second address generating means and an output; and   a fourth tristate output buffer gate having an input connected to the second data input/output of said nonvolatile static digital data storage means, an enable input connected to the output of said first inverter and an output connected to the output of said third tristate buffer.   
     
     
       16. The nonvolatile memory system of claim 13 wherein said counter means comprises: a first inverter having an input for receiving said third reset signal and an output;   a first D flip-flop having a data input connected to a logic one signal, a clock input for receiving said system clock signal, a clear input connected to the output of said first inverter and a not Q output;   a second flip-flop having a data input, a clock input for receiving said system clock signal, a clear input connected to the not Q output of said first flip-flop, a not Q output connected to the data input of said second D flip-flop and a Q output;   a third D flip-flop having a data input, a clock input connected to the Q output of said second flip-flop, a clear input connected to the not Q output of said first flip-flop, a not Q output connected to the data input of said third D flip-flop and a Q output;   a second inverter having an input connected to the not Q output of said first flip-flop and an output for providing said first reset signal;   a first NOR gate having a first input for receiving said system clock signal, a second input connected to the not Q output of said first flip-flop, a third input connected to the Q output of said second flip-flop, a fourth input connected to the Q output of said third flip-flop and an output;   a second NOR gate having a first input for receiving said system clock signal, a second input connected to the not Q output of said second flip-flop, a third input connected to the not Q output of said third flip-flop and an output for providing said PHI1 clock signal;   a third NOR gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop, a third input connected to the not Q output of said third flip-flop and an output for providing said PHI2 clock signal;   a fourth NOR gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop, a third input connected to the Q output of said third flip-flop and an output;   a fifth NOR gate having a first input connected to the not Q output of said flip-flop, a second input for receiving said system clock signal, a third input and an output for providing said PHI012 clock signal;   a NAND gate having a first input for receiving said system clock signal, a second input connected to the Q output of said second flip-flop and an output; and   a third inverter having an input connected to the output of said NAND gate and an output connected to the third input of said fifth NOR gate.   
     
     
       17. The nonvolatile memory system of claim 13 wherein said first address generating means comprises: ten first through tenth negative edge triggered J K flip-flops, each of said J K flip-flops having a J input connected to a logic one signal, a K input connected to said logic one signal, a clock input, a preset input, a clear input and a Q output;   the clock input of said first JK flip-flop receiving said PHI012 clock signal;   the Q output of said first JK flip-flop being connected to the clock input of said second J K flip-flop, the Q output of said second J K flip-flop being connected to the clock input of said third J K flip-flop, the Q output of said third J K flip-flop being connected to the clock input of said fourth J K flip-flop, the Q output of said fourth J K flip-flop being connected to the clock input of said fifth J K flip-flop, the Q output of said fifth J K flip-flop being connected to the clock input of said sixth J K flip-flop, the Q output of said sixth J K flip-flop being connected to the clock input of said seventh J K flip-flop, the Q output of said seventh J K flip-flop being connected to the clock input of said eighth J K flip-flop, the Q output of said eighth J K flip-flop being connected to the clock input of said ninth J K flip-flop and the Q output of said ninth J K flip-flop being connected to the clock input of said tenth J K flip-flop;   first through tenth load circuits, each of said load circuits having a data input, a reset input for receiving said first reset signal, a load input for receiving said parallel load signal, a data input, a preset output and a clear output;   the data inputs of said first and second load circuits being connected to a logic zero and the data inputs of said third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to first, second, third, fourth, fifth, sixth, seventh and eighth Q outputs of said second program instruction storage means;   the preset outputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the preset inputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth J K flip-flop; and   the clear outputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the clear inputs of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth J K flip-flops.   
     
     
       18. The nonvolatile memory system of claim 17 wherein each of said load circuits comprises: a first NAND gate having a first input for receiving said first reset signal, a second input and an output;   a second NAND gate having a first input for receiving said first reset signal, a second input and an output;   an inverter having an input for receiving said parallel load signal and an output connected to the second input of said second nand gate;   a third NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said second NAND gate and an output connected to the clear input of a respective one of said J K flip-flops; and   a fourth NAND gate having a first input for receiving said parallel load signal, an output connected to the present input of a respective one of said J K flip-flops and a second input;   the second inputs of first and fourth NAND gates of said first and second load circuits being connected to said logic zero signal and the second inputs of the first and fourth NAND gates of said third, fourth, fifth, sixth, seventh, eighth, ninth and tenth load circuits being respectively connected to the first, second, third, fourth, fifth, sixth, seventh and eighth Q outputs of said second program instruction storage means.   
     
     
       19. The nonvolatile memory system of claim 13 wherein each of said first, second and third program instruction storage means comprises eight negative edge triggered D flip-flops. 
     
     
       20. The nonvolatile memory system of claim 13 wherein said second address generating means comprises: first through eleventh negative edge triggered J K flip-flops, each of said J K flip-flops having a J input connected to a logic one signal, a K input connected to said logic one signal, a preset input connected to said logic one signal, a clock input, a clear input and a Q output;   the clock input of said first J K flip-flop receiving said increment address generating means clock signal;   clear input of each of said J K flip-flops receiving said second reset signal;   the Q output of said first J K flip-flop being connected to the clock input of said second J K flip-flop, the Q output of said second J K flip-flop being connected to the clock input of said third J K flip-flop, the Q output of said third J K flip-flop being connected to the clock input of said fourth J K flip-flop, the Q output of said fourth J K flip-flop being connected to the clock input of said fifth J K flip-flop, the Q output of said fifth J K flip-flop being connected to the clock input of said sixth J K flip-flop, the Q output of said sixth J K flip-flop being connected to the clock input of said seventh J K flip-flop, the Q output of said seventh J K flip-flop being connected to the clock input of said eighth J K flip-flop, the Q output of said eighth J K flip-flop being connected to the clock input of said ninth J K flip-flop, the Q output of said ninth J K flip-flop being connected to the clock input of said tenth J K flip-flop and the Q output of said tenth J K flip-flop being connected to the clock input of said eleventh J K flip-flop.   
     
     
       21. The nonvolatile memory system of claim 13 wherein said flip-flop means comprises a negative edge triggered D type flip-flop. 
     
     
       22. The nonvolatile memory system of claim 13 wherein at least one of the program instructions latched within said third program instruction storage means when supplied to and decoded by said control circuit means will result in said control circuit means providing said read/write digital logic signal to said nonvolatile static digital data storage means.