Fan-out semiconductor package

Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.

What is claimed is: 
     
       1. A fan-out semiconductor package comprising:
 a first interconnection member having a through-hole; 
 a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; 
 an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and 
 a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, 
 wherein the side surface of the semiconductor chip has a step portion, and 
 the side surface of the semiconductor chip has a staircase-shaped cross section by the step portion. 
 
     
     
       2. The fan-out semiconductor package of  claim 1 , wherein the step portion is formed so that a width of the active surface is smaller than that of the inactive surface. 
     
     
       3. The fan-out semiconductor package of  claim 1 , wherein the encapsulant encapsulates at least portions of the first interconnection member and inactive surface of the semiconductor chip. 
     
     
       4. The fan-out semiconductor package of  claim 1 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
 the first and second redistribution layers are electrically connected to the connection pads. 
 
     
     
       5. The fan-out semiconductor package of  claim 4 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
 the third redistribution layer is electrically connected to the connection pads. 
 
     
     
       6. The fan-out semiconductor package of  claim 4 , wherein a distance between the redistribution layer of the second interconnection member and the first redistribution layer is greater than that between the redistribution layer of the second interconnection member and the connection pad. 
     
     
       7. The fan-out semiconductor package of  claim 4 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member. 
     
     
       8. The fan-out semiconductor package of  claim 5 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip. 
     
     
       9. The fan-out semiconductor package of  claim 1 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
 the first to third redistribution layers are electrically connected to the connection pads. 
 
     
     
       10. The fan-out semiconductor package of  claim 9 , wherein the first interconnection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
 the fourth redistribution layer is electrically connected to the connection pads. 
 
     
     
       11. The fan-out semiconductor package of  claim 9 , wherein the first insulating layer has a thickness greater than that of the second insulating layer. 
     
     
       12. The fan-out semiconductor package of  claim 9 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member. 
     
     
       13. The fan-out semiconductor package of  claim 9 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip. 
     
     
       14. A fan-out semiconductor package, comprising:
 a first interconnection member having a through-hole; 
 a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; 
 an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and 
 a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, 
 wherein the side surface of the semiconductor chip, connecting the active surface and the inactive surface, has two or more step portions. 
 
     
     
       15. The fan-out semiconductor package of  claim 14 , wherein the encapsulant encapsulates at least portions of the first interconnection member and inactive surface of the semiconductor chip. 
     
     
       16. The fan-out semiconductor package of  claim 14 , wherein the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
 the first and second redistribution layers are electrically connected to the connection pads. 
 
     
     
       17. A fan-out semiconductor package comprising:
 a first interconnection member having a through-hole; 
 a semiconductor chip disposed in the through-hole, and having an active surface having connection pads disposed thereon, an inactive surface opposing the active surface, and a side surface connecting the active surface and the inactive surface; 
 an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and 
 a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, 
 wherein at least a portion of the semiconductor chip has a width in a direction parallel to the active surface different from a width of another portion of the semiconductor chip in the direction parallel to the active surface, and 
 the first interconnection member includes a first insulating layer, a first redistribution layer in contact with the second interconnection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, 
 the first and second redistribution layers are electrically connected to the connection pads, 
 the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and 
 the third redistribution layer is electrically connected to the connection pads. 
 
     
     
       18. The fan-out semiconductor package of  claim 17 , wherein a width of the active surface of the semiconductor chip is smaller than that of the inactive surface thereof. 
     
     
       19. The fan-out semiconductor package of  claim 17 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip. 
     
     
       20. The fan-out semiconductor package of  claim 16 , wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
 the third redistribution layer is electrically connected to the connection pads.