Method and apparatus to minimize switching noise disturbance

Abstract

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive.

The invention claimed is: 
     
       1. A power management circuit, comprising:
 a main reference voltage circuit operative to generate a main reference voltage; 
 a plurality of regulator voltage reference circuits, each configured to receive the main reference voltage and each operative to output a predetermined voltage when in an enabled state; 
 wherein each regulator voltage reference circuit comprises:
 a voltage setting circuit operative to generate the predetermined voltage from the main reference voltage; 
 a first current limiting transistor in series with the voltage setting circuit; 
 a second current limiting transistor; 
 a switching network connecting the first current limiting transistor and the second current limiting transistor; and 
 a control circuit operative to:
 switch the regulator voltage reference circuit from a disabled state to a pre-charge state; 
 switch the regulator voltage reference circuit from the pre-charge state to the enabled state; 
 
 
 wherein, in the pre-charge state, the first current limiting transistor and the second current limiting transistor are connected in a current mirror configuration; and 
 wherein, in the enabled state, the second current limiting transistor is disconnected from the first current limiting transistor. 
 
     
     
       2. The power management circuit of  claim 1 :
 wherein each regulator voltage reference circuit further comprises a current source; and 
 wherein, when the voltage reference circuit is in the pre-charge state, a limited current supplied to the voltage setting circuit is proportional to a pre-charge bias current generated by the current source. 
 
     
     
       3. The power management circuit of  claim 1 , wherein the voltage setting circuit comprises a resistive voltage dividing network. 
     
     
       4. The power management circuit of  claim 1 , wherein, when the voltage reference circuit is in the disabled state, a current from the reference voltage input to the voltage setting circuit is interrupted. 
     
     
       5. The power management circuit of  claim 1 , wherein, when the voltage reference circuit is in the pre-charge state, the current mirror configuration is operative to decrease a slew rate of the predetermined voltage output signal. 
     
     
       6. The power management circuit of  claim 1 :
 wherein the first current limiting transistor and the second current limiting transistor are paired on silicon; and 
 wherein the size of the first current limiting transistor is a multiple of the size of the second current limiting transistor. 
 
     
     
       7. The power management circuit of  claim 6 , wherein a gate width of the first current limiting transistor is a multiple of the size of a gate width of the second current limiting transistor. 
     
     
       8. A method of selectively enabling a regulator voltage reference circuit adapted to receive a main reference voltage from a main reference voltage circuit and operative to output a predetermined voltage when in an enabled state;
 wherein the regulator voltage reference circuit comprises:
 a voltage setting circuit operative to generate the predetermined voltage from the main reference voltage; 
 a first current limiting transistor in series with the voltage setting circuit; 
 a second current limiting transistor; 
 a switching network connecting the first current limiting transistor and the second current limiting transistor; and 
 a control circuit; 
 
 the method comprising:
 switching the regulator voltage reference circuit from a disabled state to a pre-charge state in which the first current limiting transistor and the second current limiting transistor are connected in a current mirror configuration; and 
 switching the regulator voltage reference circuit from the pre-charge state to the enabled state in which the second current limiting transistor is disconnected from the first current limiting transistor. 
 
 
     
     
       9. The method of  claim 8 :
 wherein the regulator voltage reference circuit comprises a current source; and 
 wherein the method comprises supplying, when the voltage reference circuit is in the pre-charge state, a limited current to the voltage setting circuit that is proportional to a pre-charge bias current generated by the current source. 
 
     
     
       10. The method of  claim 8 :
 wherein the voltage setting circuit comprises a resistive voltage dividing network; and 
 wherein the method comprises providing an output voltage from the regulator voltage reference circuit using the resistive voltage dividing network. 
 
     
     
       11. The method of  claim 8 , further comprising, when the voltage reference circuit is in the disabled state, interrupting a current from the reference voltage input to the voltage setting circuit. 
     
     
       12. The method of  claim 8 , further comprising, when the voltage reference circuit is in the pre-charge state, operating the current mirror configuration to decrease a slew rate of the predetermined voltage output signal. 
     
     
       13. An electronic device, comprising:
 a power management circuit, comprising:
 a main reference voltage circuit operative to generate a main reference voltage; 
 a plurality of regulator voltage reference circuits, each adapted to receive the main reference voltage and each operative to output a predetermined voltage when in an enabled state; 
 wherein each regulator voltage reference circuit comprises:
 a voltage setting circuit operative to generate the predetermined voltage from the main reference voltage; 
 a first current limiting transistor in series with the voltage setting circuit; 
 a second current limiting transistor; 
 a switching network connecting the first current limiting transistor and the second current limiting transistor; and 
 a control circuit operative to:
 switch the regulator voltage reference circuit from a disabled state to a pre-charge state; 
 switch the regulator voltage reference circuit from the pre-charge state to the enabled state; 
 
 
 wherein, in the pre-charge state, the first current limiting transistor and the second current limiting transistor are connected in a current mirror configuration; and 
 wherein, in the enabled state, the second current limiting transistor is disconnected from the first current limiting transistor. 
 
 
     
     
       14. The electronic device of  claim 13 , wherein the electronic device is a wireless communications device.