Semiconductor device

Abstract

To reduce power consumption of a shift register. A semiconductor device includes a shift register. The shift register includes a plurality of stages. Any one of the stages includes first to fourth switches and a sequential circuit. The first switch and the second switch are electrically connected to each other in parallel between a first wiring and a second wiring. The third switch and the fourth switch are electrically connected to each other in series between a third wiring and the second wiring. The first wiring has a function of transmitting a clock signal. The third wiring has a function of transmitting a potential corresponding to a high or low level of the clock signal. A signal of the second wiring or a signal in accordance with the signal of the second wiring is input to a sequential circuit.

The invention claimed is: 
     
       1. A semiconductor device comprising a shift register,
 wherein the shift register comprises a plurality of stages, 
 wherein one of the plurality of stages comprises a first switch, a second switch, a third switch, a fourth switch, a first transistor, and a sequential circuit, 
 wherein the first switch and the second switch are electrically connected to each other in parallel between a first wiring and a second wiring, 
 wherein the third switch, the fourth switch, and the first transistor are electrically connected to one another in series between a third wiring and the second wiring, 
 wherein a clock signal is input to the first wiring, 
 wherein a potential corresponding to one of a high level and a low level of the clock signal is input to the third wiring, 
 wherein on/off of the first switch and the third switch is controlled in accordance with a first signal, 
 wherein on/off of the second switch and the fourth switch is controlled in accordance with a second signal, and 
 wherein the sequential circuit holds the first signal or the second signal in accordance with a third signal of the second wiring. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the first signal is an output signal from a previous stage of the one stage, and 
 wherein the second signal is an output signal from a subsequent stage of the one stage. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein the first signal is input to the third switch via a first inverter, and 
 wherein the second signal is input to the fourth switch via a second inverter. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the first signal is input to the third switch via a first NAND circuit, and 
 wherein the second signal is input to the fourth switch via a second NAND circuit. 
 
     
     
       5. The semiconductor device according to  claim 1 , wherein when the first wiring and the second wiring are in conduction, the third wiring and the second wiring are in non-conduction. 
     
     
       6. The semiconductor device according to  claim 1 , further comprising a second transistor,
 wherein one terminal of the third switch is electrically connected to one of a source and a drain of the first transistor, and 
 wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. 
 
     
     
       7. A semiconductor device comprising a shift register,
 wherein the shift register comprises a plurality of stages, 
 wherein one of the plurality of stages comprises a first switch, a second switch, a third switch, a fourth switch, a first transistor, a second transistor, and a sequential circuit, 
 wherein the first switch and the second switch are electrically connected to each other in parallel between a first wiring and a second wiring, 
 wherein the third switch, the fourth switch, and the first transistor are electrically connected to one another in series between a third wiring and the second wiring, 
 wherein a fourth wiring and the second wiring are connected via the second transistor, 
 wherein a gate of the first transistor is electrically connected to a gate of the second transistor, 
 wherein a clock signal is input to the first wiring, 
 wherein a potential corresponding to one of a high level and a low level of the clock signal is input to the third wiring, 
 wherein a potential corresponding to the other of the high level and the low level of the clock signal is input to the fourth wiring, 
 wherein on/off of the first switch and the third switch is controlled in accordance with a first signal, 
 wherein on/off of the second switch and the fourth switch is controlled in accordance with a second signal, and 
 wherein the sequential circuit holds the first signal or the second signal in accordance with a third signal of the second wiring. 
 
     
     
       8. The semiconductor device according to  claim 7 ,
 wherein the first signal is an output signal from a previous stage of the one stage, and 
 wherein the second signal is an output signal from a subsequent stage of the one stage. 
 
     
     
       9. The semiconductor device according to  claim 7 ,
 wherein the first signal is input to the third switch via a first inverter, and 
 wherein the second signal is input to the fourth switch via a second inverter. 
 
     
     
       10. The semiconductor device according to  claim 7 ,
 wherein the first signal is input to the third switch via a first NAND circuit, and 
 wherein the second signal is input to the fourth switch via a second NAND circuit. 
 
     
     
       11. The semiconductor device according to  claim 7 , wherein when the first wiring and the second wiring are in conduction, the third wiring and the second wiring are in non-conduction. 
     
     
       12. A semiconductor device comprising a stage,
 wherein the stage comprises a first switch, a second switch, a third switch, and a fourth switch, a first transistor, 
 wherein the first switch and the second switch are electrically connected to each other in parallel between a first wiring and a second wiring, 
 wherein the third switch, the fourth switch, and the first transistor are electrically connected to one another in series between a third wiring and the second wiring, 
 wherein a control terminal of the first switch is electrically and directly connected to a fourth wiring and a control terminal of the third switch is electrically connected to the fourth wiring via a first inverter, and 
 wherein a control terminal of the second switch is electrically and directly connected to a fifth wiring and a control terminal of the fourth switch is electrically connected to the fifth wiring via a second inverter. 
 
     
     
       13. The semiconductor device according to  claim 12 ,
 wherein a clock signal is input to the first wiring, and 
 wherein a potential corresponding to one of a high level and a low level of the clock signal is input to the third wiring. 
 
     
     
       14. The semiconductor device according to  claim 12 ,
 wherein the fourth wiring outputs a first signal as an output signal from a previous stage of the stage, and 
 wherein the fifth wiring outputs a second signal as an output signal from a subsequent stage of the stage. 
 
     
     
       15. The semiconductor device according to  claim 12 , wherein when the first wiring and the second wiring are in conduction, the third wiring and the second wiring are in non-conduction. 
     
     
       16. The semiconductor device according to  claim 12 , further comprising a second transistor,
 wherein one terminal of the third switch is electrically connected to one of a source and a drain of the first transistor, and 
 wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor.