Array substrate, method for manufacturing the same, and display device

Abstract

A method for manufacturing an array substrate, including steps of forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate, and subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, so as to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region.

What is claimed is: 
     
       1. A method for manufacturing an array substrate, comprising steps of:
 forming a semiconductor pattern, a gate electrode and a first insulation pattern sequentially on a base substrate at different layers, the semiconductor pattern being insulated from the gate electrode, an orthogonal projection of the semiconductor pattern onto the base substrate covering an orthogonal projection of the first insulation pattern onto the base substrate, and the orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate; and 
 subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, to form an active layer, a heavily-doped source electrode region, a lightly-doped source electrode region, a heavily-doped drain electrode region, and a lightly-doped drain electrode region, 
 wherein subsequent to the ion implantation, an orthogonal projection of the active layer onto the base substrate fully overlaps the orthogonal projection of the gate electrode onto the base substrate, orthogonal projections of the lightly-doped source electrode region and the lightly-doped drain electrode region onto the base substrate overlap the orthogonal projection of the first insulation pattern onto the base substrate rather than the orthogonal projection of the gate electrode onto the base substrate, and orthogonal projections of the heavily-doped source electrode region and the heavily-doped drain electrode region onto the base substrate do not overlap the orthogonal projection of the first insulation pattern onto the base substrate and the orthogonal projection of the gate electrode onto the base substrate. 
 
     
     
       2. The method according to  claim 1 , further comprising forming a storage capacitor including an upper polar plate, a lower polar plate, and a second insulation pattern for separating the upper polar plate from the lower polar plate, wherein the lower polar plate is made of an identical material and arranged at an identical layer to the gate electrode, and the first insulation pattern is made of an identical material and arranged at an identical layer to the second insulation pattern. 
     
     
       3. The method according to  claim 2 , further comprising:
 forming the semiconductor pattern on the base substrate; 
 forming a first insulation layer on the base substrate with the semiconductor pattern; 
 forming the gate electrode and the lower polar plate made of an identical material and arranged at an identical layer on the base substrate with the first insulation layer; 
 forming the first insulation pattern and the second insulation pattern made of the second insulation layer on the base substrate with the gate electrode and the lower polar plate, the first insulation pattern covering the gate electrode, and the second insulation pattern covering the lower polar plate; 
 subjecting the semiconductor pattern to ion implantation through a single ion implantation process using the first insulation pattern and the gate electrode as a mask plate, to form the active layer, the heavily-doped source electrode region and the lightly-doped source electrode region, and the heavily-doped drain electrode region and the lightly-doped drain electrode region; and 
 forming the upper polar plate on the second insulation pattern. 
 
     
     
       4. The method according to  claim 3 , wherein the first insulation layer is made of silicon dioxide and/or silicon nitride, and has a thickness of 500 Å to 2000 Å. 
     
     
       5. The method according to  claim 4 , wherein the first insulation layer has a thickness of 600 Å to 1500 Å. 
     
     
       6. The method according to  claim 3 , wherein a patterning process for forming the first insulation pattern and the second insulation pattern and a patterning process for forming the upper polar plate use a same mask plate. 
     
     
       7. The method according to  claim 3 , wherein the gate electrode is made of molybdenum and/or aluminum, and has a thickness of 1000 Å to 5000 Å. 
     
     
       8. The method according to  claim 2 , wherein a patterning process for forming the first insulation pattern and the second insulation pattern and a patterning process for forming the upper polar plate use a same mask plate. 
     
     
       9. The method according to  claim 8 , wherein the gate electrode is made of molybdenum and/or aluminum, and has a thickness of 1000 Å to 5000 Å. 
     
     
       10. The method according to  claim 8 , wherein the first insulation layer is made of silicon dioxide and/or silicon nitride, and has a thickness of 500 Å to 2000 Å. 
     
     
       11. The method according to  claim 2 , wherein the gate electrode is made of molybdenum and/or aluminum, and has a thickness of 1000 Å to 5000 Å. 
     
     
       12. The method according to  claim 1 , wherein the gate electrode is made of molybdenum and/or aluminum, and has a thickness of 1000 Å to 5000 Å. 
     
     
       13. The method according to  claim 12 , wherein the gate electrode has a thickness of 1500 Å to 4000 Å. 
     
     
       14. The method according to  claim 1 , wherein the ion implantation is performed using a gas containing boron and/or phosphorus as an implantation media, at an implantation energy of 10 to 200 KeV and at an implantation dosage of 1*1011 to 1*1020 atoms/cm3. 
     
     
       15. An array substrate, comprising:
 a base substrate, 
 a thin film transistor (TFT) formed on the base substrate, the TFT comprising a gate electrode, a source electrode, a drain electrode and an active layer, the source electrode comprising a heavily-doped source electrode region and a lightly-doped source electrode region, and the drain electrode comprising a heavily-doped drain electrode region and a lightly-doped drain electrode region; 
 a first insulation pattern arranged above the gate electrode, and an orthogonal projection of the first insulation pattern onto the base substrate covering an orthogonal projection of the gate electrode onto the base substrate; and 
 a storage capacitor formed on the base substrate, 
 wherein an orthogonal projection of the active layer onto the base substrate fully overlaps the orthogonal projection of the gate electrode onto the base substrate, orthogonal projections of the lightly-doped source electrode region and the lightly-doped drain electrode region onto the base substrate overlap the orthogonal projection of the first insulation pattern onto the base substrate rather than the orthogonal projection of the gate electrode onto the base substrate, and orthogonal projections of the heavily-doped source electrode region and the heavily-doped drain electrode region onto the base substrate do not overlap the orthogonal projection of the first insulation pattern onto the base substrate and the orthogonal projection of the gate electrode onto the base substrate, 
 wherein the storage capacitor comprises an upper polar plate, a lower polar plate, a second insulation pattern for separating the upper polar plate from the lower polar plate, the lower polar plate is made of an identical material and arranged at an identical layer to the gate electrode, and the first insulation pattern is made of an identical material and arranged at an identical layer to the second insulation pattern. 
 
     
     
       16. The array substrate according to  claim 15 , wherein the gate electrode is made of molybdenum and/or aluminum, and has a thickness of 1000 Å to 5000 Å. 
     
     
       17. The array substrate according to  claim 16 , wherein the gate electrode has a thickness of 1500 Å to 4000 Å. 
     
     
       18. The array substrate according to  claim 15 , wherein the lower polar plate and the gate electrode is each of a structure consisting of one, two or more layers. 
     
     
       19. A display device, comprising the array substrate according to  claim 15 .