Oxide semiconductor device with an oxygen-controlling insulating layer

Abstract

Provided is a highly reliable semiconductor device which includes a transistor including an oxide semiconductor. The semiconductor device includes an oxide semiconductor layer; a gate insulating layer provided over the oxide semiconductor layer; a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween; an insulating layer being in contact with part of an upper surface of the oxide semiconductor layer, covering a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer, and having a lower oxygen-transmitting property than the gate insulating layer; a sidewall insulating layer provided on the side surface of the gate electrode layer with the insulating layer provided therebetween; a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer.

What is claimed is: 
     
       1. A semiconductor device comprising:
 an oxide semiconductor layer in which a channel formation region of a transistor is localized; 
 a gate electrode layer over the oxide semiconductor layer and overlapping with the oxide semiconductor layer; 
 a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode layer; and 
 a first insulating layer on and in contact with a part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface of the gate electrode layer, 
 wherein the gate insulating layer includes an oxygen-excess region, 
 wherein the first insulating layer has a lower oxygen-transmitting property than the gate insulating layer, and 
 wherein the first insulating layer has a thickness greater than or equal to 5 nm and less than or equal to 10 nm. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the gate insulating layer comprises silicon and oxygen, and 
 wherein the first insulating layer comprises aluminum and oxygen. 
 
     
     
       3. The semiconductor device according to  claim 1 , wherein, in the vicinity of the gate electrode layer, a dielectric environment of a source region side of the oxide semiconductor layer is substantially identical to a dielectric environment of a drain region side of the oxide semiconductor layer. 
     
     
       4. A semiconductor device comprising:
 an oxide semiconductor layer in which a channel formation region of a transistor is localized; 
 a gate electrode layer over the oxide semiconductor layer and overlapping with the oxide semiconductor layer; 
 a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode layer; 
 a first insulating layer on and in contact with a part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer; and 
 a second insulating layer on the side surface of the first insulating layer, 
 wherein side end portions of the first insulating layer are aligned with side end portions of the second insulating layer, 
 wherein the gate insulating layer includes an oxygen-excess region, 
 wherein the first insulating layer has a lower oxygen-transmitting property than the gate insulating layer, and 
 wherein the first insulating layer has a thickness greater than or equal to 5 nm and less than or equal to 10 nm. 
 
     
     
       5. The semiconductor device according to  claim 4 , wherein the first insulating layer is a metal oxide film. 
     
     
       6. The semiconductor device according to  claim 4 , wherein the first insulating layer is an aluminum oxide film. 
     
     
       7. A memory device including the semiconductor device according to  claim 4 . 
     
     
       8. The semiconductor device according to  claim 4 , further comprising a third insulating layer covering the oxide semiconductor layer, the gate electrode layer, the first insulating layer, and the second insulating layer. 
     
     
       9. The semiconductor device according to  claim 8 , further comprising a source electrode layer and a drain electrode layer of the transistor on and in contact with the third insulating layer and in electrical contact with the oxide semiconductor layer. 
     
     
       10. The semiconductor device according to  claim 9 , wherein the semiconductor device is configured so that, in the vicinity of the gate electrode layer, dielectric characteristics of portions overlapping the oxide semiconductor layer and comprised between the oxide semiconductor layer and the third insulating layer are substantially identical on a source side of the oxide semiconductor layer with respect to the gate electrode layer and on a drain side of the oxide semiconductor layer with respect to the gate electrode layer. 
     
     
       11. A semiconductor device comprising:
 an oxide semiconductor layer which is non-single-crystal and includes a crystalline component, and in which a channel formation region of a transistor is localized; 
 a gate electrode layer over the oxide semiconductor layer and overlapping with the oxide semiconductor layer; 
 a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode layer; 
 a first insulating layer on and in contact with a part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer; and 
 a second insulating layer on the side surface of the first insulating layer, 
 wherein side end portions of the first insulating layer are aligned with side end portions of the second insulating layer, 
 wherein the gate insulating layer includes an oxygen-excess region, 
 wherein the first insulating layer has a lower oxygen-transmitting property than the gate insulating layer, and 
 wherein the first insulating layer has a thickness greater than or equal to 5 nm and less than or equal to 10 nm. 
 
     
     
       12. The semiconductor device according to  claim 11 , wherein in the crystalline component, a c-axis is aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of a surface of the oxide semiconductor layer. 
     
     
       13. The semiconductor device according to  claim 11 , wherein the first insulating layer is a metal oxide film. 
     
     
       14. The semiconductor device according to  claim 11 , wherein the first insulating layer is an aluminum oxide film. 
     
     
       15. A memory device including the semiconductor device according to  claim 11 . 
     
     
       16. The semiconductor device according to  claim 11 , further comprising a third insulating layer covering the oxide semiconductor layer, the gate electrode layer, the first insulating layer, and the second insulating layer. 
     
     
       17. The semiconductor device according to  claim 16 , further comprising a source electrode layer and a drain electrode layer of the transistor on and in contact with the third insulating layer and in electrical contact with the oxide semiconductor layer. 
     
     
       18. The semiconductor device according to  claim 17 ,
 wherein the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor layer, 
 wherein, in regions of the oxide semiconductor layer in direct contact with the source electrode layer and the drain electrode layer, a ratio of a content of the crystalline component to a content of an amorphous component is lower than in a region overlapping with the gate insulating layer. 
 
     
     
       19. The semiconductor device according to  claim 17 , wherein the semiconductor device is configured so that, in the vicinity of the gate electrode layer, dielectric characteristics of portions overlapping the oxide semiconductor layer and comprised between the oxide semiconductor layer and the third insulating layer are substantially identical on a source side of the oxide semiconductor layer with respect to the gate electrode layer and on a drain side of the oxide semiconductor layer with respect to the gate electrode layer.