US9844079B1ActiveUtility

Method and system of triggering signal analysis combining time and frequency domain trigger criteria

Individually held — no corporate assignee on recordPriority: Oct 27, 2010Filed: Oct 27, 2010Granted: Dec 12, 2017
Est. expiryOct 27, 2030(~4.3 yrs left)· nominal 20-yr term from priority
H04W 76/005H04W 24/08H04W 4/10H04W 48/16H04L 67/12H04W 76/45
34
PatentIndex Score
0
Cited by
17
References
18
Claims

Abstract

A signal analyzer comprises: a first tuner configured to tune to a first frequency band and to output first tuner data; a memory device configured to store the first tuner data; a spectrum calculator configured to calculate a series of spectra for the first tuner data; a processor configured to determine a presence of a transmission of interest within the first tuner data based on the series of spectra; a second tuner configured to receive the first tuner data stored in the memory device and to tune to a second frequency band including the transmission of interest. The second tuner outputs second tuner data in response to the stored first tuner data. The signal analyzer also comprises a transmission start time detector configured to receive the second tuner data and to determine a start time for the transmission of interest from the second tuner data.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A signal analyzer, comprising:
 a first tuner configured to tune to a first frequency band and to output first tuner data; 
 a memory device configured to store the first tuner data; 
 a spectrum calculator configured to calculate a series of spectra for the first tuner data; 
 a processor configured to determine when a transmission of interest is present within the first tuner data based on the series of spectra; 
 a second tuner configured to receive the first tuner data stored in the memory device and to tune to a second frequency band including the transmission of interest, wherein the second tuner outputs second tuner data in response to the first tuner data; and 
 a transmission start time detector configured to receive the second tuner data and to determine a start time for the transmission of interest from the second tuner data, wherein the transmission start time detector comprises a magnitude trigger configured to receive the second tuner data and to compare the second tuner data to one or more trigger criteria. 
 
     
     
       2. The signal analyzer of  claim 1 , wherein in response to a comparison of the second tuner data with the one or more trigger criteria, the transmission start time detector is configured to output a trigger signal to the processor indicating the start time for the transmission of interest. 
     
     
       3. The signal analyzer of  claim 2 , wherein the processor is configured to respond to the trigger signal to cause the memory device to replay to the second tuner a portion of the first tuner data stored in the memory device beginning at a selected memory location corresponding to the start time for the transmission of interest, and to receive a portion of the second tuner data corresponding to the transmission of interest. 
     
     
       4. The signal analyzer of  claim 3 , wherein the processor is further configured to perform a signal analysis on the portion of the second tuner data corresponding to the transmission of interest. 
     
     
       5. The signal analyzer of  claim 1 , wherein the transmission start time detector comprises the processor. 
     
     
       6. The signal analyzer of  claim 1 , further comprising a data processor configured to overlap the first tuner data and to provide the overlapped first tuner data to the spectrum calculator. 
     
     
       7. The signal analyzer of  claim 1 , further comprising a spectral data combiner configured to perform at least one of an averaging operation, a peak hold operation, and a combining operation on the series of spectra. 
     
     
       8. The signal analyzer of  claim 1 , wherein the processor comprises a general purpose digital microprocessor executing a software algorithm. 
     
     
       9. The signal analyzer of  claim 1 , wherein the processor comprises one of a programmable gate array and an application specific integrated circuit. 
     
     
       10. A method, comprising:
 tuning a first tuner to a first frequency band and outputting first tuner data from the first tuner; 
 storing the first tuner data in a memory device; 
 calculating a series of spectra for the first tuner data; 
 determining when a transmission of interest is present within the first tuner data based on the series of spectra; 
 tuning a second tuner to a second frequency band including a frequency of the transmission of interest; 
 providing the first tuner data from the memory device to the second tuner, and in response thereto outputting second tuner data; 
 determining a start time for the transmission of interest from the second tuner data; 
 overlapping the first tuner data to provide overlapped first tuner data; and 
 calculating the series of spectra from the overlapped first tuner data. 
 
     
     
       11. The method of  claim 10 , further comprising performing at least one of an averaging operation, a peak hold operation, and a combining operation on the series of spectra. 
     
     
       12. The method of  claim 10 , wherein determining a start time for the transmission of interest from the second tuner data comprises comparing the second tuner data to one or more trigger criteria. 
     
     
       13. The method of  claim 12 , further comprising in response to comparing the second tuner data to the one or more trigger criteria, outputting a trigger signal indicating the start time for the transmission of interest. 
     
     
       14. The method of  claim 10 , further comprising generating a trigger signal indicating the start time for the transmission of interest. 
     
     
       15. The method of  claim 14 , further comprising, in response to the trigger signal, causing the memory device to provide to the second tuner a portion of the first tuner data stored in the memory device beginning at a selected memory location corresponding to the start time for the transmission of interest, and to output from the second tuner a portion of the second tuner data corresponding to the transmission of interest. 
     
     
       16. The method of  claim 15 , further comprising performing a signal analysis on the portion of the second tuner data corresponding to the transmission of interest. 
     
     
       17. The method of  claim 14 , further comprising in response to the trigger signal, causing the memory device to provide to the second tuner a portion of the first tuner data stored in the memory device beginning at a selected memory location corresponding to a selected delay after the start time for the transmission of interest, and to output from the second tuner a portion of the second tuner data corresponding to the transmission of interest. 
     
     
       18. The method of  claim 17 , further comprising performing a signal analysis on the portion of the second tuner data corresponding to the transmission of interest.

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