Vertical metal insulator metal capacitor having a high-K dielectric material

Abstract

A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM capacitor has a first electrode, a second electrode, and a high-k capacitor dielectric material disposed therebetween. The dielectric constant of the capacitor dielectric material is greater than the dielectric constant of interlayer dielectric (ILD) material. After ILD is removed from between the vertically-oriented, interdigitated portions of the first and second electrodes, a capacitor dielectric material having a dielectric constant greater than the ILD dielectric material is disposed therebetween.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a plurality of inter-level dielectric layers over a substrate; and 
 a vertical metal-insulator-metal (MIM) capacitor, comprising:
 a first electrode comprising:
 a first conductive plate horizontally-oriented and parallel to a substrate, and 
 a first group of conductive structures physically and electrically connected to the first conductive plate, and vertically-oriented with respect to the substrate; 
 
 a second electrode comprising:
 a second conductive plate horizontally-oriented and parallel to the substrate, and 
 a second group of conductive structures physically and electrically connected to the second conductive plate, and vertically-oriented with respect to the substrate; and 
 
 a high-k dielectric material disposed between the first and second electrodes, wherein the high-k dielectric material is disposed within a recess formed through the plurality of inter-level dielectric layers, and has a dielectric constant higher than a dielectric constant of each of the plurality of inter-level dielectric layers. 
 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the high-k dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ). 
     
     
       3. The integrated circuit of  claim 1 , wherein the first group of conductive structures and the second group of conductive structures are arranged in a matrix of rows and columns. 
     
     
       4. The integrated circuit of  claim 1 , further comprising a second high-k dielectric material disposed between the first electrode and the second electrode. 
     
     
       5. The integrated circuit of  claim 4 , wherein the second high-k dielectric material is deposited using CVD, and the high-k dielectric material is deposited using ALCVD. 
     
     
       6. The integrated circuit of  claim 1 , wherein the high-k dielectric material is chosen from the group consisting of aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ), hafnium silicate (HfSiO 4 ), lanthanum oxide (La 2 O 3 ), silicon nitride (SiN), strontium oxide (SrO), titanium dioxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), and zirconium silicate (ZrSiO 4 ). 
     
     
       7. The integrated circuit of  claim 1 , wherein the first group of conductive structures and the second group of conductive structures include metal pads connected by vias. 
     
     
       8. An integrated circuit, comprising:
 a substrate; 
 a plurality of field effect transistors (FETs); 
 a plurality of inter-level dielectric layers formed over the plurality of field effect transistors; 
 a first electrode of a vertical metal-insulator-metal (MIM) capacitor comprising:
 a first conductive plate horizontally-oriented and parallel to the substrate, and 
 a first group of conductive structures vertically-oriented with respect to the substrate, the first group of conductive structures being physically and electrically connected to the first conductive plate; 
 
 a second electrode of the vertical MIM capacitor comprising:
 a second conductive plate horizontally-oriented and parallel to the substrate, and 
 a second group of conductive structures vertically-oriented with respect to the substrate, the second group of conductive structures being physically and electrically connected to the second conductive plate; and 
 
 a second dielectric material disposed between the first electrode and the second electrode, the second dielectric material being disposed in a recess formed through the plurality of inter-level dielectric layers and having a higher dielectric constant than each of the plurality of inter-level dielectric layers. 
 
     
     
       9. The integrated circuit of  claim 8 , wherein the second dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ). 
     
     
       10. The integrated circuit of  claim 8 , wherein each of the plurality of inter-level dielectric layers has a dielectric constant less than or equal to a dielectric constant of SiO 2 . 
     
     
       11. The integrated circuit of  claim 8 , wherein the first group of conductive structures and the second group of conductive structures are arranged in a matrix of rows and columns. 
     
     
       12. The integrated circuit of  claim 8 , wherein the first group of conductive structures and the second group of conductive structures include metal pads connected by vias. 
     
     
       13. An integrated circuit, comprising:
 a plurality of inter-level dielectric layers over a substrate; and 
 a capacitor, comprising:
 a first electrode comprising:
 a first conductive plate horizontally-oriented and parallel to the substrate, and 
 a first group of conductive structures physically and electrically connected to the first conductive plate, and vertically-oriented with respect to the substrate; 
 
 a second electrode comprising:
 a second conductive plate horizontally-oriented and parallel to the substrate, and 
 a second group of conductive structures physically and electrically connected to the second conductive plate, and vertically-oriented with respect to the substrate; and 
 
 a dielectric material disposed between the first and second electrodes, wherein the first group of conductive structures is interdigitated with the second group of conductive structures, and the dielectric material has a dielectric constant greater than 3.9, and wherein the dielectric material is different from each of the plurality of inter-level dielectric layers. 
 
 
     
     
       14. The integrated circuit of  claim 13 , wherein the dielectric material is chosen from the group consisting of aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ), hafnium silicate (HfSiO 4 ), lanthanum oxide (La 2 O 3 ), silicon nitride (SiN), strontium oxide (SrO), titanium dioxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), and zirconium silicate (ZrSiO 4 ). 
     
     
       15. The integrated circuit of  claim 13 , wherein the first group of conductive structures and the second group of conductive structures are arranged in a matrix of rows and columns. 
     
     
       16. The integrated circuit of  claim 13 , further comprising a second dielectric material disposed between the first electrode and the second electrode. 
     
     
       17. The integrated circuit of  claim 16 , wherein the second dielectric material is deposited using CVD, and the dielectric material is deposited using ALCVD. 
     
     
       18. The integrated circuit of  claim 13 , wherein the first group of conductive structures and the second group of conductive structures include metal pads connected by vias. 
     
     
       19. The integrated circuit of  claim 1 , wherein the first group of conductive structures is interdigitated with the second group of conductive structures. 
     
     
       20. The integrated circuit of  claim 13 , wherein the dielectric material is disposed within a recess formed through the plurality of inter-level dielectric layers.