Data transfer control device and memory-containing device

Abstract

An image processing module input/output port in a DMAC includes an input part which receives second address information and an addressing request signal from an image processing module and an output part which outputs a reply signal indicating valid reception of the second address information to the image processing module. The image processing module input/output port can perform signal input/output control processing of returning, in response to the addressing request signal, the reply signal indicating confirmation of valid reception of the second address information to the image processing module when valid reception of the second address information is confirmed. A memory access controller performs memory access processing of accessing a storage area to be accessed in a memory based on the first address information (=the second address information) received via the image processing module input/output port.

What is claimed is: 
     
       1. A data transfer control device that controls data transfer between a memory and a predetermined module, said predetermined module outputting an address signal group and an addressing request signal, the address signal group including a start address of a storage area to be accessed in said memory, the addressing request signal indicating a request for output of said address signal group, said data transfer control device comprising:
 an input/output port for use in communicating with said predetermined module, said input/output port including an input part which receives said address signal group and said addressing request signal, and an output part which outputs an address valid signal indicating valid reception of said address signal group, said input/output port being capable of performing signal input/output control processing of outputting, in response to said addressing request signal, said address valid signal to said predetermined module when said address signal group is validly received; and 
 a memory access controller performing memory access processing of accessing said storage area to be accessed in said memory based on said address signal group input via said input/output port. 
 
     
     
       2. The data transfer control device according to  claim 1 , wherein
 said memory access processing includes read processing of reading data from said storage area to be accessed in said memory and write processing of writing data to said storage area to be accessed in said memory, 
 said data transfer control device comprises:
 a first data transfer controller performing said read processing; and 
 a second data transfer controller performing said write processing, and 
 
 said first data transfer controller and said second data transfer controller each include said input/output port and said memory access controller independently of each other. 
 
     
     
       3. The data transfer control device according to  claim 1 , wherein
 said input/output port includes at least one signal storage holding said address signal group and said addressing request signal. 
 
     
     
       4. The data transfer control device according to  claim 1 , wherein
 said address signal group further includes an access order indication signal indicating an access order in said storage area to be accessed, and 
 said memory access controller performs said memory access processing of accessing said storage area to be accessed in accordance with the access order indicated by said access order indication signal. 
 
     
     
       5. A memory-containing device comprising:
 the memory; and 
 the data transfer control device according to  claim 1 , the data transfer control device controlling data transfer between said memory and the predetermined module.